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Visitor zshattler
Visitor
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Registered: ‎08-29-2018

Running ILA with gated clock/downsampling

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Edit: For future viewers of this thread, I would recommend checking out @leuschen's response in addition to @travisc -- I think that both are relevant depending on the situation you're facing! 

 

Hi there, first time poster with what I believed should be a straightforward question that I just haven't been able to find an answer for. 

 

I'm currently working on debugging a design in hardware and an ILA core would be a big help. In particular I would like to look at an I2C controller module that I designed, which runs off of a main 25 MHz system clock. However, the signals that I would like to view via the ILA, while synchronous to the 25 MHz main clock, are in reality only changing at a rate closer to 100 kHz (i.e., logic for the state machine controlling the I2C bus behavior). This means that if I trigger the ILA data acquisition based on the start of an I2C transaction, I would need a very large data depth in order to actually capture any sort of meaningful portion of the full transaction (a full transaction in this case meaning something like 40 bits at 100 kHz, with possibility of clock stretching further extending the time window).  

 

With this in mind, is there any way that I can effectively downsample the data being captured as to allow me to view a full I2C transaction using the ILA without having to use a huge data depth? One of my coworkers has suggested using a gated version of the 25 MHz clock which seems straightforward and reasonable, but based on other forum responses it seems that only free-running clocks can be provided as inputs to the ILA without any error. Additionally, is there any way that I can do this from the IP Core Wizard? I realize that you can use the wizard to specify the clock domain of the signals of interest, but it doesn't appear to give the option of actually choosing what clock is used (seemingly just defaulting to the main driver clock of the given clock domain, instead, based on the schematic). 

 

Thank you in advance for any advice provided, I've done a lot of research into this and read over just about every version of the Programming and Debugging Tutorial that I could find and just haven't been able to find a satisfactory solution. Please let me know if my question is unclear in any way, and thanks again!

 

Best, 

 

Zach

 

Edit: I'm currently using Vivado 2018.2 and using the latest release of the standalone hardware manager, if that helps! 

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Moderator
Moderator
677 Views
Registered: ‎10-19-2011

Re: Running ILA with gated clock/downsampling

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No there isnt a built in function that does this. Down sampling the the clock will most likely get you into trouble with the debug hub clocking requirements. In the past i have seen customer do a secondary HDL module helps track occurrences. Then you would trigger on this secondary occurrence. However it sounds like you want to capture some of the data sequence, so this might not work for you unless you combined this with a repetitive trigger, and multiple dumps. I dont know what your exact trigger match would be, but you could do multiple captures instead of just trying to capture the whole sequence in one go.
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4 Replies
Moderator
Moderator
678 Views
Registered: ‎10-19-2011

Re: Running ILA with gated clock/downsampling

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No there isnt a built in function that does this. Down sampling the the clock will most likely get you into trouble with the debug hub clocking requirements. In the past i have seen customer do a secondary HDL module helps track occurrences. Then you would trigger on this secondary occurrence. However it sounds like you want to capture some of the data sequence, so this might not work for you unless you combined this with a repetitive trigger, and multiple dumps. I dont know what your exact trigger match would be, but you could do multiple captures instead of just trying to capture the whole sequence in one go.
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Visitor zshattler
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656 Views
Registered: ‎08-29-2018

Re: Running ILA with gated clock/downsampling

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Thanks for the reply travisc. For now I think just making the data depth deeper will work/be easiest for me despite being a bit unnecessary, but I'll keep your advice in mind for the future. 

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Visitor leuschen
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Registered: ‎09-24-2018

Re: Running ILA with gated clock/downsampling

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You can accomplish a gated clock in the ILA by using the capture settings in the Hardware Manager ILA GUI.  In settings; set the capture mode to BASIC (rather than always), number of windows to 1, window data depth to however many gated clock samples you wish to acquire, and trigger position to 1.  Keep the trigger setup the same as you normally would.  Set the capture setup to include your gate signal for your clock and whatever condition you want the clock to acquire a sample (for example:  clock_gate == R) would take a sample every rising edge of your clock_gate signal ... synchronous to your main clock.  Once you get that running you can play around with other settings for number of windows, trigger position  ...

 

remember to route your clock_gate signal to your ila module.

 

attached is an example jpg of a RS232 port running at 9600 baud captured with a 100MHz clock gated to every 1024th sample.  In this case I used 20 windows as I typed in putty.

Capture.JPG
Visitor zshattler
Visitor
582 Views
Registered: ‎08-29-2018

Re: Running ILA with gated clock/downsampling

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Hi @leuschen

 

That's exactly what I was looking for, thank you! After talking with one of my more experienced coworkers about how ILAs used to work, I guess I was searching for a solution a little too early in the design flow last time, haha. 

 

In the end I wound up doing something similar to what you described once I got the ILA up and running, but I appreciate the detailed explanation and pictures nonetheless. 

 

Sorry that I can't accept your answer as a solution, but I'll edit my original post to point out your comment for any future viewers of the thread. Thanks again for taking the time to make an account and respond! 

 

Best, 

Zach

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