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Scholar ronnywebers
Scholar
943 Views
Registered: ‎10-10-2014

UG908 contains contradictory information on Xilinx Virtual Cable (XVC)

I'm working on a system design based on XAPP1251  

 

Instead of a Microzed board as in the XAPP1251, I plan to use an embedded controller with ethernet. The controller will run a TCP/IP stack + xvserver.c file from XAPP1251, and provide a bit-banged JTAG interface to a Zynq US+ system.

 

With that design I hope to remotely :

 

* program the QSPI on my Zynq US+ board

* download & debug bare metal code on the ARM / R5 cores using SDK 

* debug PL design using ILA's and VIO

 

to keep things short, I want to implement my own 'Xilinx SmartLynq' cable into my end-user product. XAPP1251 looks to come close to that, but it probably is not the same (?).

 

Q1: is all the above possible using XVC / XAPP1251? 

 

Q2 : I'd like to write a custom application (not use SDK) to flash the QSPI with a U-boot through my controller. Is there any example code / app note available to accomplish this?

 

Q3: UG908 (2018.2) contains contradictory information : chapter 5 says:

 

XVC.jpg

 

so from this explanation, I somehow understand that I :

* can use 'Vivado's debug features' (what are these exactly? ILA, Virtual IO, SDK debug, ...?)

* but I cannot use the Vivado programming features (-> what are these? Download the bitstream, program the QSPI, ...?

 

however a bit further in chapter 5 I can read:

 

xvc protocol.jpg

-> so now I'm confused .... this paragraph says that XVC (implemented on a networked microcontroller) gives me the exact same possibilities as for example a Digilent HS2 cable that is directly connected to Vivado/SDK??

 

Q4) the JTAG interface in XAPP1251 misses an output to drive the PS_SRST_B pin -> isn't this necessary to support the full SDK debug functionality?

 

source: JTAG-HS3 reference manual :

The Xilinx Tools occasionally require the processor core of the Zynq-7000 to be reset during debug operations. The Zynq platform processor has a pin dedicated for this purpose (PS_SRST_B). Driving the PS_SRST_B pin low causes the processor to reset while maintaining any existing break points and watch points. The JTAG-HS3 is capable of driving this pin low under the instruction of Xilinx’s SDK during debugging operations.

 

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Xilinx Employee
Xilinx Employee
828 Views
Registered: ‎10-11-2011

Re: UG908 contains contradictory information on Xilinx Virtual Cable (XVC)

The first statement should be true stating that we don’t support programming features. 

 

It looks like these are the 3 things you want to do:

* program the QSPI on my Zynq US+ board

* download & debug bare metal code on the ARM / R5 cores using SDK 

* debug PL design using ILA's and VIO

 

  1. I don't think so.
  2. There are methods for remote PS debug but they don’t involve XVC.  I’m not familiar with this personally but I think AR64759 is probably relevant.  I wouldn’t recommend XVC for this task as I’m not aware of a way to connect the necessary debug bridge to the PS.
  3. This is definitely possible and what XVC and the debug bridge are designed to do.
Scholar ronnywebers
Scholar
811 Views
Registered: ‎10-10-2014

Re: UG908 contains contradictory information on Xilinx Virtual Cable (XVC)

@denist thanks for the answers. A few further questions :

 

1) programming is currently not supported, any chance that XVC might be improved by Xilinx in the future such that it also supports QSPI programming? It would be interesting to many customers to have such field-update feature built-into their device. It would allow for an easy 'disaster recovery' in case some update went wrong

 

2) I think you mean :

 

* using a pc with a usb-to-jtag convertor attached to it's usb port, and running hw_server : great solution during development, when you want to debug your product from a remote office.

 

But we want to go a step furhter, and  replace the PC by an embedded microcontroller with ethernet, and it's I/O pins connected to the JTAG port of the Zynq. The microcontroller would then need to run hw_server I guess ... but I'm not sure if the code for hw_server is available to customers?

  

-> basically my question is : can we build a SmartLynq solution by ourselves / on our own controller sitting next to Zynq, to put this into our product? 

 

 

* I also checked tcf_agent and the AXI JTAG uart, works great to debug linux applications - but does not allow bare metal code debug :-)

 

3) clear, thanks!

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Scholar ronnywebers
Scholar
742 Views
Registered: ‎10-10-2014

Re: UG908 contains contradictory information on Xilinx Virtual Cable (XVC)

@denist, it looks like Microblaze can be debugged over XVC :

 

source page (Xilinx website):

 

XVC solution supports many capabilities that can enhance and augment the solution based on user needs such as:

  • MDM support to allow debug of MicroBlaze systems via SDK

-> looks like it would not be that hard for Xilinx to open up ARM remote debug over XVC ? Guess such solution would need to controll the 'SRSTn' pin on the JTAG interface, so I'll connect that extra GPIO pin in case Xilinx would ever make SDK remote debug over XVC available to end-users... do you think there's any chance this will happen? Because this is going off-topic from the original subject, I created this follow-up post : will Xilinx Virtual Cable (XVC) support remote debug of the ARM cores in the future?

 

The guy in this post could even use xsct to check the status of the 6 arm cores in a Zynq US+

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Xilinx Employee
Xilinx Employee
730 Views
Registered: ‎10-11-2011

Re: UG908 contains contradictory information on Xilinx Virtual Cable (XVC)

The post has been moved in "Design Tools". Hopefully you can get some answers from XVC experts. I am a little outside my comfort zone here.