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Newbie sworld
Newbie
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Registered: ‎10-30-2014

VCC and GND pin name problem in Vivado

There seems to be a problem with the VCC and GND primitive pin names in EDIF cores in Vivado. We have been using GROUND as the pin name for the GND symbol and VCC as the pin name for the VCC symbol. These pin names work fine in ISE but give the following error messages in Vivado 2014.2 using a Zync part. The problem also occurs in version 2014.3.

[Netlist 29-181] Cell 'GND' defined in file 'play.edn' has pin 'GROUND' which is not valid on primitive 'GND'.  Instance 'U_P/I_from_net_GND' will be treated as a black box, not an architecture primitive ["C:/play/play.edn":51]

[Netlist 29-181] Cell 'VCC' defined in file 'play.edn' has pin 'VCC' which is not valid on primitive 'VCC'.  Instance 'U_P/I_from_net_VCC' will be treated as a black box, not an architecture primitive ["C:/play/play.edn":54]

We can fix the problem fairly easily by editing the EDIF cores by replacing "GROUND" with "G", "portRef  VCC" with "portRef  P" and "port  VCC" with "port  P". However, we would like to avoid having to do this if at all possible, as there is a chance we may break the design by having to do these edits.

Any chance Xilinx can fix this problem in their next version of Vivado?

Attached is a top level VHDL file and example EDIF core with the VCC and GND primitives attached to outputs via the BUF primitive.

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