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Visitor bciftci
Visitor
285 Views
Registered: ‎05-14-2018

VIO problem

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Dear all,

I put a VIO IP in my block design with a single output which is connected to an AXI GPIO and clk input being driven by the only clk source in my block design which comes from the processor. Then, I generate the bitstream and program my device with the generated bitstream and probe files. However, after that, I got the warnings in the console below:

WARNING: [Xicom 50-38] xicom: No CseXsdb register file specified for CseXsdb slave type: 0, cse driver version: 0. Slave initialization skipped.
INFO: [Labtools 27-1434] Device xc7z020 (JTAG device index = 1) is programmed with a design that has no supported debug core(s) in it.
WARNING: [Labtools 27-3123] The debug hub core was not detected at User Scan Chain 1 or 3.
Resolution: 
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active OR
2. Manually launch hw_server with -e "set xsdb-user-bscan <C_USER_SCAN_CHAIN scan_chain_number>" to detect the debug hub at User Scan Chain of 2 or 4. To determine the user scan chain setting, open the implemented design and use: get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub].
WARNING: [Labtools 27-1974] Mismatch between the design programmed into the device xc7z020_1 and the probes file C:/Users/bacif/mmc_impl/cent_cont_sepr_arm/cent_cont_sepr_arm.runs/impl_1/debug_nets.ltx.
The device design has 0 ILA core(s) and 0 VIO core(s). The probes file has 0 ILA core(s) and 1 VIO core(s).
Resolution: 
1. Reprogram device with the correct programming file and associated probes file OR
2. Goto device properties and associate the correct probes file with the programming file already programmed in the device.

Consequently, I do not see the dashboard that should contain the VIO interface.

I am not fully sure that I understood the warning message in full detail but I am sure that the bitstream and probes file are that I use are relevant to each other and there is no timing error in my design. Can you please advise me what can be the possible reason and solution method?

Thanks in advance,

Baris

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1 Solution

Accepted Solutions
Moderator
Moderator
213 Views
Registered: ‎02-09-2017

Re: VIO problem

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Hi @bciftci ,

I see you are using a Zynq device. I suspect the clock that you are using is a clock generated in the PS side and routed to the PL side.

In such cases, you need to first export your project to SDK and run a basic "Hello World" project. Within that project there will be a script called init_ps7.tcl, which will initialize all the PS resources such as memories, GPIOs, Clocks, etc.

Then, you can go back to Vivado, reprogram the bitstream into the FPGA (or you can also have SDK do it for you) and you'll be able to see the debug cores.

The document Vivado Design Suite Tutorial Embedded Processor Hardware Design - UG940, Lab 1, starting on Step 6, has a good example of the process above described.

Please let us know if that helps you.

Thanks,

Andre Guerrero

Product Applications Engineer

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2 Replies
Moderator
Moderator
214 Views
Registered: ‎02-09-2017

Re: VIO problem

Jump to solution

Hi @bciftci ,

I see you are using a Zynq device. I suspect the clock that you are using is a clock generated in the PS side and routed to the PL side.

In such cases, you need to first export your project to SDK and run a basic "Hello World" project. Within that project there will be a script called init_ps7.tcl, which will initialize all the PS resources such as memories, GPIOs, Clocks, etc.

Then, you can go back to Vivado, reprogram the bitstream into the FPGA (or you can also have SDK do it for you) and you'll be able to see the debug cores.

The document Vivado Design Suite Tutorial Embedded Processor Hardware Design - UG940, Lab 1, starting on Step 6, has a good example of the process above described.

Please let us know if that helps you.

Thanks,

Andre Guerrero

Product Applications Engineer

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Highlighted
Visitor bciftci
Visitor
203 Views
Registered: ‎05-14-2018

Re: VIO problem

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Hi @anunesgu,

Correct, I use the PL fabric clock in my block design as the main and only clock source. Although I have my own processor application, I was trying to see the VIO dashboard after I program PL in Vivado, not realizing the required clock (PL fabric clock from the processor) by VIO actually starts ticking after the PS application is run. So, as you said, after I program PL and run PS application, I'm able to see the VIO dashboard in Vivado.

Thanks for the reply,

Baris