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Observer pinewood
Observer
357 Views
Registered: ‎02-17-2019

Waveform data read from ILA core is corrupted with 250MHz Free running Debug Hub clock and 15MHz JTAG Clock

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Testing a 100G Ethernet(CAUI4) system using with Vivado 2018.3(64bit) on windows 10 Enterprise(ver.1809) and Vertex UltraScale+ VCU118 Evaluation Platform(xcv9p-flga2104-2L-e).

The Synthesis and The Implementation were completed without any errors and all clock timings are met.

But errors are occured at the transfer signals from ILA to the host as below.

INFO: [Labtools 27-1966] The ILA core 'hw_ila_1' triggered at 2019-Jun-06 16:00:31
ERROR: [Xicom 50-38] xicom: No trigger mark in any sample in window: 0.
ERROR: [Xicom 50-41] Waveform data read from ILA core is corrupted (user chain=1, slave index=11).
Resolution:
1) Ensure that the clock signal connected to the debug core and/or debug hub is clean and free-running.
2) Ensure that the clock connected to the debug core and/or debug hub meets all timing constraints.
3) Ensure that the clock connected to debug core and/or debug hub is faster than the JTAG clock frequency.
ERROR: [Xicom 50-38] xicom: Error during interpreting trace readback data
ERROR: [Labtools 27-3176] hw_server failed during internal command.
Resolution: Check that the hw_server is running and the hardware connectivity to the target

 

ILA不具合(2019-06-06).pngHardware Manager

Settings of the debug core as below that is a part of the "xdc" file.

This setting is generated by the set up debug wizard.

create_debug_core u_ila_0 ila
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
set_property C_DATA_DEPTH 8192 [get_debug_cores u_ila_0]
set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
set_property port_width 1 [get_debug_ports u_ila_0/clk]
connect_debug_port u_ila_0/clk [get_nets [list {gtwizard_wrapper0/example_wrapper_inst/gtwizard_ultrascale_0_inst/inst/gen_gtwizard_gtye4_top.gtwizard_ultrascale_0_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0]}]]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
set_property port_width 20 [get_debug_ports u_ila_0/probe0]
connect_debug_port u_ila_0/probe0 [get_nets [list {u0_pcs_100g_top_inst/reg_block_sync[0]} {u0_pcs_100g_top_inst/reg_block_sync[1]} {u0_pcs_100g_top_inst/reg_block_sync[2]} {u0_pcs_100g_top_inst/reg_block_sync[3]} {u0_pcs_100g_top_inst/reg_block_sync[4]} {u0_pcs_100g_top_inst/reg_block_sync[5]} {u0_pcs_100g_top_inst/reg_block_sync[6]} {u0_pcs_100g_top_inst/reg_block_sync[7]} {u0_pcs_100g_top_inst/reg_block_sync[8]} {u0_pcs_100g_top_inst/reg_block_sync[9]} {u0_pcs_100g_top_inst/reg_block_sync[10]} {u0_pcs_100g_top_inst/reg_block_sync[11]} {u0_pcs_100g_top_inst/reg_block_sync[12]} {u0_pcs_100g_top_inst/reg_block_sync[13]} {u0_pcs_100g_top_inst/reg_block_sync[14]} {u0_pcs_100g_top_inst/reg_block_sync[15]} {u0_pcs_100g_top_inst/reg_block_sync[16]} {u0_pcs_100g_top_inst/reg_block_sync[17]} {u0_pcs_100g_top_inst/reg_block_sync[18]} {u0_pcs_100g_top_inst/reg_block_sync[19]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
set_property port_width 2 [get_debug_ports u_ila_0/probe1]
connect_debug_port u_ila_0/probe1 [get_nets [list {PCS_LOOP0_REG[0]} {PCS_LOOP0_REG[1]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
set_property port_width 2 [get_debug_ports u_ila_0/probe2]
connect_debug_port u_ila_0/probe2 [get_nets [list {tx_mac_valid_0[0]} {tx_mac_valid_0[1]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
set_property port_width 2 [get_debug_ports u_ila_0/probe3]
connect_debug_port u_ila_0/probe3 [get_nets [list {rx_mac_valid_0[0]} {rx_mac_valid_0[1]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
set_property port_width 1 [get_debug_ports u_ila_0/probe4]
connect_debug_port u_ila_0/probe4 [get_nets [list u0_pcs_100g_top_inst/pcs_100g_rx_inst/all_am_lock]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
set_property port_width 1 [get_debug_ports u_ila_0/probe5]
connect_debug_port u_ila_0/probe5 [get_nets [list u0_pcs_100g_top_inst/pcs_100g_rx_inst/all_am_lock0]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
set_property port_width 1 [get_debug_ports u_ila_0/probe6]
connect_debug_port u_ila_0/probe6 [get_nets [list GPIO_LED4_OBUF]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7]
set_property port_width 1 [get_debug_ports u_ila_0/probe7]
connect_debug_port u_ila_0/probe7 [get_nets [list GPIO_LED5_OBUF]]
set_property C_CLK_INPUT_FREQ_HZ 250000000 [get_debug_cores dbg_hub]
set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
connect_debug_port dbg_hub/clk [get_nets clk_free_run_BUFG]

Conditions of the test are concluded as below.

  • The debug core that is designated u_ila_0 is assigned as hw_ila1.
  • The clock of u_ila_0 is PLL output of GTY Transcever's RX clock that is not clean and free-running.
  • The clock of debug hub is 250MHz provided from the evaluation platform, it is clean and free-running.
  • Frequency of the JTAG clock is 15MHz.

All of Resolutions that described in the error message [Xicom 50-41] are achieved.

Is any other resolution of these errors?

 

 

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1 Solution

Accepted Solutions
Moderator
Moderator
308 Views
Registered: ‎02-09-2017

Re: Waveform data read from ILA core is corrupted with 250MHz Free running Debug Hub clock and 15MHz JTAG Clock

Jump to solution

Hi @pinewood,

 

Thank you for the detailed explanation.

The clock for the ILA core also needs to be free-running (not just the debug hub clock). So I would initially bet that is the issue.

Are you able to clock the ILA core with the same clock that is being used for the debug_hub and test again?

Thanks,

 

Andre Guerrero

Product Applications Engineer

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3 Replies
Moderator
Moderator
309 Views
Registered: ‎02-09-2017

Re: Waveform data read from ILA core is corrupted with 250MHz Free running Debug Hub clock and 15MHz JTAG Clock

Jump to solution

Hi @pinewood,

 

Thank you for the detailed explanation.

The clock for the ILA core also needs to be free-running (not just the debug hub clock). So I would initially bet that is the issue.

Are you able to clock the ILA core with the same clock that is being used for the debug_hub and test again?

Thanks,

 

Andre Guerrero

Product Applications Engineer

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
Observer pinewood
Observer
296 Views
Registered: ‎02-17-2019

Re: Waveform data read from ILA core is corrupted with 250MHz Free running Debug Hub clock and 15MHz JTAG Clock

Jump to solution

Thank you for reply.

I tried to change ila's clock from the GTY transciver to free running clock the VCU118 board, and waveform data is not corrupted.

Frequency of the clock from the GTY transceiver faster than free-running clock from the VCU118 board, and observation results are looks proper.

When ILAs clock slower than diriving clock of observed signals, is always proper observation results?

 

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Observer pinewood
Observer
224 Views
Registered: ‎02-17-2019

Re: Waveform data read from ILA core is corrupted with 250MHz Free running Debug Hub clock and 15MHz JTAG Clock

Jump to solution

I confirmed that frequency of Free running clock which is provided to Debug Hub and ILA should be slower than driving clock frequency of signals that are observed.

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