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Adventurer
Adventurer
857 Views
Registered: ‎07-17-2017

Xilinx XPower Analyzer Confidence Level

Hello everyone.

Im using ISE Design Suite 14.7 and Xilinx XPower Analyzer to find the total power for my design.

2018-12-05_11-26-26.jpgConfidence level summaryHow can I increase the I/O nodes activity and internal nodes activity confidence level?

Thank you very much

 

 

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21 Replies
Community Manager
Community Manager
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Registered: ‎07-23-2015

Re: Xilinx XPower Analyzer Confidence Level

@dayana42200 The best way is to input a SAIF or VCD stimulus file which matches your design operation. You can set it manually as well if you don't have a VCD/SAIF file. 

Take a look at "Set Default Activity rates" and "Adjust Design Data" sections under Power Analysis using XPA here:  https://www.xilinx.com/support/documentation/sw_manuals/xilinx14_7/ug733.pdf
 

 

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Adventurer
Adventurer
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Registered: ‎07-17-2017

Re: Xilinx XPower Analyzer Confidence Level

Hello @gnarahar

Ive added the SAIF file as shown in the figure below, but the confidence level is the same. What can be done to increase the confidence level? Also I do notice that both the design nets matched and simulation nets matched is not 100%. Why is that?

2018-12-05_14-21-21.jpgProject Settings

 One more thing, based on the summary, the quiescent power is higher than the dynamic power. Should the dynamic power is higher than the quiescent power? Can you share your opinion based on your experience?

2018-12-05_14-24-06.jpgPower Result

 I also provide the files used in the xpower analyzer.

Thank you.

 

 

 

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Adventurer
Adventurer
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Registered: ‎07-17-2017

Re: Xilinx XPower Analyzer Confidence Level

@gnarahar

Hi.

Based on the power result, the login percentage is 0.

Does that mean the design is small for the dynamic power?

Thank you.

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Scholar watari
Scholar
775 Views
Registered: ‎06-16-2013

Re: Xilinx XPower Analyzer Confidence Level

Hi @dayana42200

 

According your result, it seems that toggle rate (activity rate) is very small.

So, quiescent current is larger than dynamic power.

 

I guess your test senario is questionable whether or not that is vased on reality or your design is wrong.

Would you make sure your test senario ?

 

Best regards,

 

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Adventurer
Adventurer
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Registered: ‎07-17-2017

Re: Xilinx XPower Analyzer Confidence Level

@watari

 

What is toggle rate?

What do you mean by test scenario? Is it the timing constraint?

Thank you.

 

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Scholar watari
Scholar
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Registered: ‎06-16-2013

Re: Xilinx XPower Analyzer Confidence Level

Hi @dayana42200

 

Sorry for my typo.

 

I mention again.

 

# Toggle rate

Power consumption relate to "toggle rate".

"Toggle rate" means same as "switching activity rate" and refer the following URL, if you want to know detail.

 

https://www.xilinx.com/support/documentation/sw_manuals/xilinx11/ism_c_writing_power_stimulus.htm

 

# Scenario

"SAIF (Switching Activity Interchange Format)" is used to estimate power consumption.

As above URL, this file is generated by simulation with test scenario.

 

The purpose of "Test scenario" is to define what logic is active/how to activate the logic.

Your result points out "low swiching activity rate".

 

In this case, quiescent current is larger than dynamic current.

 

BTW, if you generated SAIF by constraint file, I suggest that you define switching activity rate as  using "set_switching_activity -toggle_rate <value>(unit is [%]) -static_probability <value>(value is from 0.0 to 1.0) <target net or io and so on>"

Would you refer the following URL and page 58 ?

 

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_2/ug907-vivado-power-analysis-optimization.pdf 

 

Best regards,

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Adventurer
Adventurer
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Registered: ‎07-17-2017

Re: Xilinx XPower Analyzer Confidence Level

@watari

Yes I do generate the SAIF file based on the simulation and Ive follow the step mentioned in the link given.

Ive two query

1. If in the testbench code, is run the design till 850 ns, so Ive to run the SAIF file till 850 also?

2. If the PAR simulation doesnt show the function of the design, would the SAIF file wrong? Because I get the correct function for behavioral simulation.

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Adventurer
Adventurer
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Registered: ‎07-17-2017

Re: Xilinx XPower Analyzer Confidence Level

@watari

Ive attach .ncd, .pcf and .SAIF at the top of the post.

Would It help for you to understand what is happening in my design?

 

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Scholar watari
Scholar
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Registered: ‎06-16-2013

Re: Xilinx XPower Analyzer Confidence Level

Hi @dayana42200

 

> 1. If in the testbench code, is run the design till 850 ns, so Ive to run the SAIF file till 850 also?

 

Yes. I suspect it is wrong scenario.

I suggest you do simulation more long time.

 

> 2. If the PAR simulation doesnt show the function of the design, would the SAIF file wrong? Because I get the correct function for behavioral simulation.

 

If the result is different between netlist and behavioral simulation, it's equivalence checking issue.

Would you makre sure synthesis and routing/optimize log file ?

 

Best regards,

 

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Adventurer
Adventurer
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Registered: ‎07-17-2017

Re: Xilinx XPower Analyzer Confidence Level

@watari


If the result is different between netlist and behavioral simulation, it's equivalence checking issue.

Would you makre sure synthesis and routing/optimize log file ?


I dont understand whats in the quote.

Could you explain?

Thank you very much

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Scholar watari
Scholar
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Registered: ‎06-16-2013

Re: Xilinx XPower Analyzer Confidence Level

Hi @dayana42200

 

Someone is often facing equivalance issue between behaviour design and gate level design.

 

https://en.wikipedia.org/wiki/Formal_equivalence_checking

 

It is caused by estimating power consumption and/or different result between behaivour design and gate level design.

For example, if you have a mistake like typo or connection between layers,EDA tools remove un-used logic cone and/or degenerate by accident.

 

Thus,  the formal equivalence issue is caused by removing and/or optimizing logic cones. Then, it wrongly work.

 

BTW, in your case, according to your log file, there are mismatching points.

It might be formal equivalance issue or using incorrect design issue for power consumption.

 

So, would you make sure synthesis log file (formal quivalance issue) or the setting for power consumption  on XPower Analyzer (using incorrect design issue) ?

 

Best regards,

 

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Adventurer
Adventurer
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Registered: ‎07-17-2017

Re: Xilinx XPower Analyzer Confidence Level

@watari

I see. Now I understand.

But which log file do I used?

and how can check the errors?

Sorry if the question sound silly.

Im not familiar with analyzing log files.

Thank you.

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Adventurer
Adventurer
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Registered: ‎07-17-2017

Re: Xilinx XPower Analyzer Confidence Level

@watari

Also Ive extended the simulation time from 600 ns to 1200ns but the result is the same

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Scholar watari
Scholar
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Registered: ‎06-16-2013

Re: Xilinx XPower Analyzer Confidence Level

Hi @dayana42200

 

Sorry. I forgot detail log file name in ISE.

However you can see synthesis and place & route log files to confirm equivalent issue.

Would you share them, if possible ?

 

Also, would you share waveform of top level to make sure test scenario issue ?

 

At least, I suspect low activity rate (toggle rate) by something.

 

Best regards,

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Adventurer
Adventurer
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Registered: ‎07-17-2017

Re: Xilinx XPower Analyzer Confidence Level

@watari

Ive attached all the files and images that you wanted.

Is the files attached correct?

2018-12-16_13-54-05.jpgBehavioral Simulation

 

2018-12-16_13-55-59.jpgPost Route Simulation

 

 

 

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Scholar watari
Scholar
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Registered: ‎06-16-2013

Re: Xilinx XPower Analyzer Confidence Level

Hi @dayana42200

 

It's test scenario issue.

After 9 cycles, this design go to stable state.

So, power consumption is low,even if you run long time.

 

I suggest modifing test bench.

 

Best regard,

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Adventurer
Adventurer
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Registered: ‎07-17-2017

Re: Xilinx XPower Analyzer Confidence Level

@watari

I see

So Do I need to do?

Should I change the clock period from 40ns to 80ns

or the input is clock after the 9th clock cycle?

Thank you for your help.

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Scholar watari
Scholar
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Registered: ‎06-16-2013

Re: Xilinx XPower Analyzer Confidence Level

Hi @dayana42200

 

If your scenario is to output SCORE_Out as 14 and SS_Out as 3 (it means that your scenario is creect), your calcurated power consumption is correct.
Because of swithcing activity is very low. So that leackage power is larger than dynamic power.
I guess your logic is only active during few clock period.

If you want to ovserve power consumption by changing input signals, I suggest changing or modifying your test scenario.
After that, you can get other calculated power consumption.

It depends on what you forcus in your design.

- Compare power consumptions by different input signals ?
- Calculate worst power consumption ?
- Estimate power consumption in your test scenario ?
- and so on...

I will help you, if you show what you forcus in your design.

Best regards,

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Adventurer
Adventurer
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Registered: ‎07-17-2017

Re: Xilinx XPower Analyzer Confidence Level

@watari

I am sorry. What do you mean by creect?

Thank you.

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Scholar watari
Scholar
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Registered: ‎06-16-2013

Re: Xilinx XPower Analyzer Confidence Level

Hi @dayana42200

 

I mention about "correct" in my post.

 

From 1st post

> How can I increase the I/O nodes activity and internal nodes activity confidence level?

 

If your test scenario is "correct", you can not increase the I/O nodes activity and internal nodes activity.

Because thest scenario already finished before 9th clock cycle and so it doesn't increase the activity of I/O nodes and internal nodes.

 

So, if you want increase the I/O nodes activity and internal nodes activity, I suggest changing or modifying test scenario or adding new test scenario, if possible.

 

Best regards,

 

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Adventurer
Adventurer
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Registered: ‎07-17-2017

Re: Xilinx XPower Analyzer Confidence Level

I see. Now I understand.

Thank you for your help

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