Welcome to Design Tools Community Forum.
This community includes all boards that’s related to issues while designing with ISE and Vivado. You can go through individual board descriptions to find the most suited board for your issue. Post your question and leverage the vast community knowledge for help.
Discuss Vivado™ High-Level Synthesis and best practices for C, C++ and SystemC specifications to be directly targeted into Xilinx devices.
Discuss tools not covered by the other existing boards including Vivado Logic Analyzer, ChipScope Pro, Power Estimation tools, iMPACT, and others.
Discuss SDAccel™ development environment for OpenCL™, C, and C++ which enables application acceleration leveraging FPGAs.
Discuss TCL usage in Vivado. Users are encouraged to share their scripting examples and questions.
Discuss Xilinx tools for design entry and management, including Vivado™ IP Catalog, IP packager, Project Navigator™, Core Generator™, Schematic Entry, and other related topics.