UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Welcome to Design Tools Community Forum.
This community includes all boards that’s related to issues while designing with ISE and Vivado. You can go through individual board descriptions to find the most suited board for your issue. Post your question and leverage the vast community knowledge for help.

Community
Design Tools
Title Posts
There are no unread messages in this message board

Installation and Licensing

Discuss topics involving installation, licensing, updates, and operating system support for all products in the Vivado™ Design Suite and the ISE Design Suite™.
17595
There are no unread messages in this message board

Synthesis

Discuss topics involving HDL synthesis tools and practices, including Vivado™ Synthesis, XST™, 3rd party synthesis tools, HDL coding practices and tips.
21578
There are no unread messages in this message board

Simulation and Verification

Discuss topics involving simulation and verification tools and flows, including XSIM and ISE Simulator™, 3rd party simulators, and formal verification.
18520
There are no unread messages in this message board

Implementation

Discuss topics involving design implementation tools and practices, including Vivado™ Implementation, Translate, Map, Place and Route, SmartXplorer, and FPGA Editor.
17392
There are no unread messages in this message board

Design Entry

Discuss Xilinx tools for design entry and management, including Vivado™ IP Catalog, IP packager, Project Navigator™, Core Generator™, Schematic Entry, and other related topics.
12785
There are no unread messages in this message board

Timing Analysis

Discuss topics involving timing analysis including tools and best practices, including Timing closure and XDC Timing Analyzer™, TRACE™, Timing Constraints, and Speed Files.
Latest Topic - setting dbg_hub/clk
12179
There are no unread messages in this message board

Vivado TCL Community

Discuss TCL usage in Vivado. Users are encouraged to share their scripting examples and questions.
5059
There are no unread messages in this message board

High-Level Synthesis (HLS)

Discuss Vivado™ High-Level Synthesis and best practices for C, C++ and SystemC specifications to be directly targeted into Xilinx All Programmable devices.
9813
There are no unread messages in this message board

Design Methodologies and Advanced Tools

Discuss the UltraFast Design Methodology, Design Methodology Checklist, RTL Coding styles, Baselining, Partial Reconfiguration and Design Preservation flows, design planning tools and flows.
4203
There are no unread messages in this message board

SDAccel

Discuss SDAccel™ development environment for OpenCL™, C, and C++ which enables application acceleration leveraging FPGAs.
1306
There are no unread messages in this message board

Design Tools - Others

Discuss tools not covered by the other existing boards including Vivado Logic Analyzer, ChipScope Pro, Power Estimation tools, iMPACT, and others.
9674
Users Online
Currently online: 69 members 1,095 guests
Please welcome our newest community members: