In the previous entry in the the AI Engine Series here, we ran AIE compiler to compile the graph and kernel codes to target the AI Engine model.
In this article we will have a look at the compilation summary file in Vitis™ Analyzer which gives us a lot of useful information about the compilation.
The following article requires you to have gone through the previous articles in the AI Engine Series.
AI Engine compilation results in Vitis Analyzer
First open the project created through the previous articles.
In the project explorer window, double click on the Vitis Analyzer summary file (called project.aiecompile_summary) which is located under the Emulation-AIE compilation results (Emulation-AIE/Work).
This will open it in the Vitis Analyzer tool.
This will open a new window for the Vitis Analyzer tool. In the left panel, there are multiple sections which each provide some details about the compilation results.
Summary: Gives some high level information about the compilation such as the compile time or which command was executed
Kernel Guidance: This page gives some advice on how to optimize the graphs and kernels
Graph: This page give details about the graphs and kernels. It includes a visual representation of the graph and tables with information about the different elements in the graph
Array: Shows the actual placement of the graph in the AI Engine Array
Constraints: Summarizes the different constraints applied on the graph/kernels (if any)
Mapping Analysis: Gives a detailed mapping report of the different cores, memory and ports used by the graph
DMA Analysis: Shows all of the DMAs instantiated in the mapping, the associated port instances, and the memory groups accessed by the DMA.
Lock Allocation: Shows the different locks used for the DMAs
Log: Includes the full compilation log which can be filtered by Error, Warning, Info, and Status messages
Core Compilation: Shows the detailed logs of the compilation of each individual AI Engine core.
The graph and the array views are the most interesting when starting with the AI Engine so let's have a closer look.
Open the Graph page.
On the top of the graph page, you can see a graphic representation of the AIE graph with the different elements grouped together (you can find out later in the article how to change the grouping).
In the screenshot below, the elements are grouped by tiles.
We can see that there are 3 tiles used:
tile [24,0] (the tile located on the 25th column of the 1st row)
tile [25,0] (the tile located on the 26th column of the 1st row)
tile [25,1] (the tile located on the 26th column of the 2nd row)
The two kernels (first and second) are located on the same tile (tile [25,0]), which means that they will run sequentially on the same core, sharing the processing time of this core. The memory banks these kernel are accessing are located on different tiles (tile [24,0] and tile [25,1]) which are neighboring tiles of the tile they are running on and so they can be accessed directly by the kernels without the need for any DMA.
The memory buffers between the input port of the graph and the first kernel and between the second kernel and the output port of the graph are double buffers (these can be identified by the 2 names per memory (for example, buf0 and buf0d)). This allows the kernel to be working on one buffer while the other is filled (or emptied) by the platform.
The memory buffer between the first and second kernels is a single buffer memory (buf1). There is no need for a double buffer because the two kernels are running sequentially, so they will not access the memory at the same time.
You can change how the elements are grouped by clicking on the settings wheel on the top right corner. For example you can group by subgraphs:
Changing the view can be helpful to gain more of an understanding of the application and how it is mapped to the AI Engine array.
At the bottom of the page, you can find tables showing details about the different elements in the graph (kernels, PL, Buffers, Ports, Nets and Tiles)
It is useful to note that the tables and the graph view are linked. Selecting an element in the table highlights it in the graph view.
Open the Array page.
On the top page, we can see the view of the full array of the device (400 AIE tiles for the device on the VCK190) with the different elements of the graph placed on it.
On the bottom of the page, there are the same tables as on the graph page which are also linked to the array view.
This page might be useful to understand the latency introduced by different locations of the kernels/memory.
In the next article we will see how to generate traces to analyze the state of the of the AI Engine during simulation.