cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 

Versal GTY - how to combine Simplex TX/RX cores for several quads in IP Integrator

eschidl
Xilinx Employee
Xilinx Employee
3 0 885

To create a transceiver setup for several quads for Versal it is recommended to start with the transceiver bridge IP, choose your settings there and then let Vivado create the necessary quads for this setup through block automation.

The bridge IP allows for only one setup. So, how is it possible to have separate setups for TX and RX in the same transceiver?

Some examples of how to do this are shown below. Some cases will be supported by the block automation, some will require a bit more handiwork.

 

Example 1: One RX and one TX core with 8 lanes each, placed in two quads

 

First create a project for a Versal device and open a block design:

1.png2.png

In the block design add a transceiver bridge IP and configure it:

3.png4.png

Here the Aurora template is chosen and Simplex TX is selected for 8 lanes.

Then go into the ‘Transceiver Configs’ and select the line rate and PLL to use:

5.png

Then run the ‘Block Automation’ for this transceiver bridge IP:

6.png

You will now get a setup for this core:

7.png

Now add another transceiver bridge IP.

Here ‘JESD204 64B66B’ is chosen with Simplex RX, also for 8 lanes:

8.png9.png

You can see that the line rate and PLL selection are different for this RX setup.

Run Block Automation for this new transceiver bridge IP:

10.png11.png

You can see that both transceiver bridge IPs are connected to the same quad IPs above.

12.png

When you look into the transceiver quad IP you can see that the protocols for the two simplex setups are transferred to quad IPs.

We are now done with this example.

For the next step you would only need to set the locations for the quads as usual.

 

Example 2: One RX and three TX cores with 12 lanes together, placed in three quads.

 

This will be a setup with a 12 lane Aurora RX core (12Gbps and RPLL) and 3 TX cores with 4 lanes each:

  • One with the default raw setup at 12Gbps and TXPI control
  • One with 8B10B encoding and 6Gbps
  • One with 23Gbps and 64B66B encoding (synchronous gearbox).

 

After creating the project and block design, first create an RX core for 12 lanes with Aurora 64B66B, using RPLL:

13.png

Now run Block Automation:

14.png

You can see the RX bridge core with three quad IPs.

Create the first TX core like this:

15.png

Run Block Automation and you can see the following:

16.png

The TX core is connected to one of the quad IPs.

If you want to use the lanes of another quad you would need to manually change the highlighted connections plus clock and control signals to this other quad.

You would also need to move the TX protocols between these quads. You can leave this for now.

 

Add the second TX core:

17.png

With the Block and Connection Automation you get the following:

18.png

You can see that the block automation chooses the next quad to connect the four lanes.

Again, if you wanted the other quad to be used you would need to manually change the connections and protocol.

Add the third TX core:

19.png

Run Block and Connection Automation:

20.png

Again, the block automation uses the free quad to connect the TX lanes.

You could now validate the BD and implement this as usual by setting the location constraints.