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Video Series 27: Getting started with the Video Processing Subsystem IP

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Introduction to the Video Processing SubSystem (VPSS) IP core


The Xilinx Video Processing SubSystem IP core is a collection of video processing IPs packaged into a single IP for ease of use. This core is an HLS based IP. This means that this core is written in C/C++ and then converted to RTL (VHDL/Verilog) in the background by Vivado when you add the IP to a design.

The VPSS IP supports multiple video processing features such as the following:

  • Deinterlacing
  • Video Scaling (up and down scaling)
  • Color Space Conversion
  • Frame Rate Conversion

The VPSS IP is included for free in Vivado 2018.3 and later versions.

For documentation about the VPSS IP, refer to its Product Guide, (PG231)

Advice #1: Start with the (Hardware) example design

This Video Series entry is intended as a guide for any user starting off with the VPSS IP.

As I mentioned, the VPSS IP is based on HLS and includes multiple cores.

This introduces some complexity and rules that the user will need to follow. This is not complicated but to start quickly, the best method is to refer to the example design for both the hardware and the software design.

Generating the hardware (Vivado) example design, is easy.

(Note: these steps are documented under "Detailed Example Design" on page 67 of (PG231))

  1. Open Vivado (the 2018.3 version in my case)

  2. Create a new project for one of the supported boards (KC705, ZCU102, ZCU104 or ZCU106)
  • Note 1: If you are using a Vivado webpack edition, only the ZCU104 board will be available.
  • Note 2: It does not really matter if you have the board or not. The example design is only used as a reference. You can just recreate it for your own board.
  1. Create a block design (BD) and add the Video Processing Subsystem IP. Save the block design.

  2. In the sources window, right click on the IP and select Generate Example Design.




  1. Select the path where you would like to generate the example design.


Note: A common issue which occurs while generating the VPSS is a path issue when using a Windows OS. If you are using a Windows host OS, make sure that you are using the shortest path possible for the example design (and any of your projects in general).


In the Vivado design, the most important thing to look at is the reset signal from the VPSS which is controlling both upstream (TPG) and downstream (AXI4S to video out) IPs.

This signal is mainly useful for holding off upstream IPs from sending data until the VPSS is configured and ready to accept new data. Because the VPSS is an HLS based IP, it is important to make sure that the first data coming in is the first pixel of a frame.

Note: Because of this reset signal, each time the configuration change in the VPSS IP, the upstream IPs connected by this reset might need to be re-configured.




Also, it is interesting to note that the example design does not output video data on the board. The way the design checks that the VPSS is working is by confirming that the AXI4-Stream to Video out IP locks, meaning that the resolution set in the VTC and the number of pixels/lines outputted from the VPSS match.

Note: The video clock is not adjusted to the video resolution and is fixed to 150MHz. As a result, outputting the video data on the board would not work correctly. However, this clock is enough to show that the VPSS can be fast enough to accommodate a 1080p stream in 1 pixel per clock (PPC) configuration.

If you need to generate the software application example design, you will need to generate the BD output products for the BD (right click on the BD in the sources window > generate output products) and select to export the Hardware (File export Hardware).

Note: If you want to run the design on your board, you will also need to generate the bitstream for the design and check the “include bitstream” option when exporting the hardware.  

Advice #2: Refer to the software example application


Before you write your own application, it is better to start with the VPSS application example design as a reference.

To generate this application example design:

  1. Open SDK and set the workspace into the .sdk folder of the example design.

  2. Create a new Hardware platform specification:
    1. File > New > Other > Xilinx > Hardware Platform Specification
    2. Click Browse and select the .hdf file generated from the VPSS Vivado example design, then click finish.




Note: This step (2.) is not required if you launched SDK from the Vivado VPSS example project (it will be done automatically).

  1. Create a new BSP: Select File > New > Board Support Package. Keep the default settings for the BSP and click finish.

  2. Under the BSP folder, double click on the system.mss file to open it if it is not already opened.




  1. In the system.mss file, find the line corresponding to the video processing subsystem and click on Import Examples.




  1. In the Examples window, select the video processing subsystem example (xv_procss_example) and click OK.




To run the application

  1. Connect a USB cable from the host PC to the USB JTAG port. Ensure the appropriate device drivers are installed.

  2. Connect a second USB cable from the host PC to the USB UART port. Ensure that USB UART drivers have been installed.

Note: On a ZCU104 board, only one USB cable is required for both UART and JTAG.

  1. Connect the evaluation board to the power supply slot.

  2. Switch on the board.

  3. Start a terminal program (for example, Hyper Terminal) on the host PC with the following settings for the Standard COM port:
  • Baud Rate: 115200
  • Data Bits: 8
  • Parity: None
  • Stop Bits: 1
  • Flow Control: None
  1. Right click on the application in the project explorer and select Build Project.

  2. Right click on the application and select Run As > Run configurations.




  1. In the Run Configurations window, right click on Xilinx C/C++ application (System Debugger) and select New.




  1. Enable Program FPGA. If targeting a ZCU102/ZCU104/ZCU106 board, make sure that Run psu_init is enabled.




  1. Click Run to program the FPGA and launch the application on the board.

  2. The example application will run two use-cases and should report that the test was successful.




Advice #3: Refer to the API documentation

The Video Processing Subsystem IP is expected to be configured and controlled using the driver APIs (even though the register map is documented for debugging purposes in (PG231), direct access to the registers is not supported).

Make sure that you are familiar with all of the APIs available and that you understand their use by looking at the API documentation. To open the documentation, click on the Documentation link corresponding to the VPSS in the system.mss file (under the BSP)




Advice #4: Use the VPSS log for debugging

One important line in the example application is the line which display the log in the UART:


If you are experiencing issues with the VPSS, you will really want to use this function as it can give you a good insight into why the VPSS is not working properly (wrong configuration, system stopped, etc.)

Refer to the application example design and the API documentation for more details on how to use this function.

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