Showing results for 
Show  only  | Search instead for 
Did you mean: 

Video Series 28: Using the VPSS IP in Color Space Converter mode

3 0 2,487


In previous video series entries, I discussed the common color spaces for Image and Video; RGB (Video Series 2), YCbCr4:4:4 (Video Series 9) and YCbCr4:2:2/YCbCr4:2:0 (Video Series 10).

The Video Processing Subsystem IP includes a Color Space Converter (CSC) sub-core which allows you to convert a video stream from one of these color spaces to any of the others.

In this Video Series entry, we will see how to add the VPSS IP configured as a Color Space Converter Only.


Tutorial – Adding the VPSS in CSC only mode to a video pipeline

Note: This tutorial is intended to be used only with Vivado 2018.3 and only with the Zynq®-7000 SoC ZC702 Evaluation Kit

Testing the base design

The base design is based on the design created in Video Series entry 24. The Video pipeline is the following:

Test Pattern Generator (TPG) > AXI VDMA > AXI4 Stream to Video Out (AXI4SVidOut)

In this configuration, the TPG IP is sending YCbCr422 to the VDMA.



We will start by making sure that the design is working by rebuilding the application from the HDF file.

  1. Download the tutorial files and unzip the folder

  2. Start the Xilinx Software Command Line Tool (XSCT) 2018.3
  • From the Windows menu select the following:

Start > All Programs > Xilinx Design Tools > Xilinx Software Command Line Tool 2018.3

  • From the command line do the following:

Use the command xsct (the environment variables for SDK 2018.1 needs to be set)

  1. In xsct, cd to XVES_0028/sw. Then enter the following command:
source create_SW_proj.tcl
  1. Open SDK and select XVES_0028/sw/sdk_workspace as the workspace

  2. Build the application (Project > Build All), program the FPGA (Xilinx > Program FPGA) and launch the application (right click on the application > Run As > Launch on Hardware (System Debugger)).

You should see a pattern generated on the monitor.

  1. Close the Xilinx SDK

Add the VPSS IP in CSC Only mode to the design

Now, we will try to add the VPSS IP configured in CSC Only mode to the design between the TPG IP and the AXI VDMA IP.

  1. Open Vivado 2018.3

  2. In the Tcl console, cd into the unzipped directory (cd XVES_0028/hw)

  3. In the Tcl console, source the script tcl (source ./create_proj.tcl)

  4. When the project is built, delete the AXI4-Stream interface from the TPG IP to the AXI4-Stream Subset converter IP. This is where we will add the VPSS IP

  5. Right click on the Block Design (BD) and Click Add IP. Find the VPSS IP (search for Video Processing Subsystem) and add it to the design

  6. Double click on the VPSS IP to open its configuration GUI.

    Configure it as follows:
    • Samples per clock: 1
    • Maximum Data Width: 8
    • Video Processing Functionality: Color Space Conversion Only
    • Color Space Support: RGB | YUV 4:4:4 | YUV 4:2:2 | YUV 4:2:0


  1. Connect the AXI4-Stream interface to the TPG and AXI4-Stream Subset converter IP.



  1. Click on Run Connection Automation to let Vivado automatically connect the remaining interfaces of the VPSS IP.



  1. Validate the Block Design (BD). You should have no errors or warnings. Save the BD and then generate it.

  2. When the output product generation is over, run Synthesis, then Implementation and Generate the Bitstream

  3. Export the Hardware to SDK. Click File > Export > Export Hardware



  1. Make sure Include Bitstream is enabled and change the export location to XVES_0028/sw/sdk_export. When asked if you want to overwrite the previous exported file, click Yes



  1. Launch SDK from Vivado (File > Launch SDK)

  2. Select XVES_0028/sw/sdk_export as the export location and XVES_0028/sw/sdk_workspace as the workspace


Update the SDK application

  1. In SDK, we can check that the hardware platform was updated by opening the system.hdf file. It should list the VPSS IP in the register map



We can now update the code to configure and start the VPSS IP

  1. Copy the source file XVES_0028\final\src\ vpss_csc_example.c and paste it to replace the one in XVES_0028\sw\sdk_workspace\vpss_csc_app\src

  2. In SDK, press F5 to refresh the source files

  3. Build the application (Project > Build All), program the FPGA (Xilinx > Program FPGA) and launch the application (right click on the application > Run As > Launch on Hardware (System Debugger)).

You should still see the same pattern as in the original design. The main difference is that here the test pattern generator is outputting YCbCr444 data (configured on line 27 of the code). This video stream is then converted to YCbCr422 to be used by the ADV7511.

One of the advantages of the VPSS for color space conversion is that it can do any to any color space conversion without needing a new bitstream in the PL. We can test other configurations.

  1. On line 27 of the main source file (vpss_csc_example.c), change the color space of the video stream generated by the TPG IP to another color space (XVIDC_CSF_YCRCB_422, XVIDC_CSF_YCRCB_420 or XVIDC_CSF_RGB)
XVidC_ColorFormat colorFmtIn = XVIDC_CSF_RGB;
  1. Re-Build the application (Project > Build All), program the FPGA (Xilinx > Program FPGA) and launch the application (right click on the application > Run As > Launch on Hardware (System Debugger)).

All of the configurations should give the same pattern on the monitor.