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Vivado Design Entry Chronicles - High Level Synthesis (HLS)

Xilinx Employee
Xilinx Employee
2 0 305

This blog entry is the third lab in a series targeted at beginners in FPGA design entry using Vivado.

This third lab covers IP and RTL generation from C++ input using the High Level Synthesis (HLS) flow.

Csynthesis_hls.JPGVivado HLS flow






Each step includes a screen shot for the user to refer to as they try it out.

Steps to follow:

1. Launch Vivado HLS.


2. Click on Create New Project button to create the project.


3. Enter the Project name (proj) and location, then click Next.

projname.pngClick Browse to navigate to the location you prefer for the project and click OK. In this case, the project directory is proj and it is located in the HLS folder

4. Click Add Files, select the dut.cpp file, and click OK.


5. Click the Browse button to specify count_toggle as the Top Function.

Click OK, then Next.


6. Skip the Add/Remove C-based testbench files, then click Next.


7. To select your device, click the button highlighted below:


Select the Boards tab, search for zcu102, then select the board that appears here (Zynq UltraScale+ ZCU102 Evaluation Board) and click OK.


8. Click the Finish button to complete Vivado HLS project creation.


9. Now you should see dut.cpp added to the project(proj) under Source in the project Explorer tab.


Double click on dut.cpp under source in the project Explorer to view the content. 


10. C Synthesis:

Synthesize the C++ design into an RTL design and review the synthesis report.

Click on "Run C Synthesis" or from the menu select Solution > Run C Synthesis > Active Solution


11.The console pane confirms the completion of C Synthesis:


rtl.PNGRTL Generated after C Synthesis can be seen in explorer window under syn folder

12. The Performance Estimates, Utilization Estimates, and Interface details are populated automatically after C Synthesis.

performance.pngIn the Performance Estimates pane, you can see that the clock period is set to 10 ns. Vivado HLS targets a clock period of Clock Target minus Clock Uncertainty.

utilization.pngThe resource utilization numbers are estimates because RTL synthesis might be able to perform additional optimizations, and these figures might change after RTL synthesis.


Interface.pngThe Interface section shows the ports and I/O protocols created by interface synthesis.

13. Export RTL:

Package the design as an IP block for use in other tools in Vivado Design Suite. 

Click Export RTL or from the menu select Solution > Export RTL:


14. In the "Export RTL as IP" dialog box, ensure that the Format Selection drop-down menu shows IP Catalog, then click OK.

export_rtl_dialog.pngThe IP packager creates a package for the Vivado IP Catalog. (Other options available from the drop-down menu allow you to create IP packages for System Generator for DSP, a Synthesized Checkpoint format for Vivado).

15. The console pane will confirm completion of the Export RTL command:


Expand Solution1 in the Explorer and then expand the impl folder.

You will see the Packaged IP (xilinx_com_hls_count_toggle_1_0.zip) highlighted in the ip folder ready to be added to the Vivado IP Catalog. 

16. Add HLS IP to Vivado Project (IP Catalog).

Launch Vivado IDE and click on Create Project 


17. The New Project wizard will appear, Click Next.

Provide the project name and the location where you want this project to be created, then click Next


18.Select RTL Project for the Project Type and Click Next.


19. In Add Sources, you can Add RTL files to the project or create them. Click on Next (In this project we will be adding top level RTL at a later stage).

20. In Add Constraints, you can add constraints files to the project. Click on Next (In this project we will be adding a .xdc file at a later stage).

21.In Default Part, you can select an FPGA part or board for your project.

Click on the Boards tab, search for ZCU102 and then select ZCU102 Evaluation Board. Click Next.


22. In New Project Summary click on Finish.

23. Add HLS IP to an IP Repository.

In the Project Manager area of the Flow Navigator pane, click Settings icon.



24. In the Settings window , expand the IP under Project Settings and select Repository


Click on Add to select the IP exported from HLS.

25. In the IP Repositories Dialog:

Browse to the HLS IP exported directory (/scratch/Blog/HLS/proj/solution1/impl/ip) and click Select to close the IP Repositories window.




In the Add Repository select the IP and click OK. Click Apply and OK to exit the IP Repositirty dialog box.

26. Now you should see User Repositorty in the IP Catalog window, under which the HLS IP is added.


27. Use count_toggle IP in the vivado project created.

Double click on the count_toggle IP in the IP catalog > User Repository > VIVADO HLS IP > count_toggle


Click OK.

28.  The IP Generate Output Products dialog box will appear, in which you can select Global or "Out of Context per IP" under Synthesis Options.

Select Out of Context per IP (this is the default option) and click Generate.


29. In the next pop-up click OK. IP output products will now be generated.

30. Once the IP output products have been generated, you will be able to see the generated files in the sources window in the IP tab.

Under the instantiation template, you can see <component_name>.vho/<component_name>.veo files.

This code needs to be inserted in your vhdl/verilog file for this IP to be instantiated.


31. In the top.v RTL attached here, this core is already instantiated.

The RTL describes a simple free-running 32 bit counter. Once the counter reaches its max value, a flip-flop is toggled. This flop is connected to the output. All the functionality is included in the count_toggle IP.

A differential Buffer is used (IBUFDS) to connect a differential pair of clocks whose output is used in the design. 


32. Click on Add Sources under Project Manager.



33. In the Add Sources window, select Add or Create design sources and click on Next.


34. Click on Add files and then provide the top.v file attached here. Click Finish


35. Click on Add Sources under Project Manager.


36. Select Add or Create constraints and Click Next.


37. Click Add files and upload the top.xdc provided here, then click Finish.


38. In Project Management Click Generate Bitstream.


39. You will see the following prompt:


Click on Yes.

A "Launch Runs" pop-up will appear. Click OK.

This will launch Synthesis followed by implementation, and generate the bitstream.

Our lab is now done.

XDC File Contents:

The XDC file contains the following:


Reason for use of IBUFDS:

The reason why we have used IBUFDS is that the board we have chosen requires a differential clock.

Each board will have its own specific pin LOCs and the System Clock frequencies that it can support.

This board can support 300Mhz and 125Mhz, so we are using 125Mhz and the Pin LOC which corresponds to it. The output is connected to an LED which is LOC'ed at AG14. The last 2 statements are used to specify the IOSTANDARD for the ports.