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Vivado Design Entry Chronicles - IP Design Entry

Xilinx Employee
Xilinx Employee
2 0 613

This blog entry is the second lab in a series targeted at beginners in FPGA design entry using Vivado.

This second lab covers design entry using IP.  Each step includes a screen shot for the user to refer to as they try it out.

1.  Launch Vivado IDE.

2. In the Vivado GUI Click on Create Project:


3.  The New project wizard will appear.

Provide the project name and the location where you want this project to be created, then click Next.


4. Select RTL Project for the Project Type and Click Next.


5. In Add Sources, you can Add RTL files to the project or create them. Click on Next (In this project we will be adding top level RTL at a later stage).

6. In Add Constraints, you can add constraints files to the project. Click on Next (In this project we will be adding a .xdc file at a later stage).

7.In Default Part, you can select an FPGA part or board for your project.

Click on the Boards tab, search for ZCU102 and then select ZCU102 Evaluation Board. Click Next.


8. In New project summary click on Finish.

9. In Flow Navigator click on IP catalog (You can use IP catalog to customize and add IP into your design).


10. In this lab we will be customising and adding a Binary Counter IP to our design. In the IP catalog, search for counter and then select the Binary Counter IP.


11. The Customize IP wizard will appear. In this wizard you can provide the name for the component and configure your counter width, up/down counter, etc.

Provide the component name of your choice (by default it is c_counter_binary_0) and select an output width of 32.


12. Leave all other options at their defaults and click OK.

13. The IP Generate Output Products dialog box will appear, in which you can select Global or "Out of Context per IP" under Synthesis Options.

Select Out of Context per IP (this is the default option) and click Generate.


14. In the next pop-up click OK. IP output products will now be generated.

15. Once the IP output products have been generated, you will be able to see the generated files in the sources window in the IP tab.

Under the instantiation template, you can see <component_name>.vho/<component_name>.veo files.

This code needs to be inserted in your vhdl/verilog file for this IP to be instantiated.


16. In the top.v RTL attached here, this core is already instantiated.

The RTL describes a simple free-running 32 bit counter. This 32 bit counter functionality is implemented using a Counter IP.

Once the counter reaches its max value, a flip-flop is toggled. This flop is connected to the output.

A differential Buffer is used (IBUFDS) to connect a differential pair of clocks whose output is used in the design. 


17. Click on Add Sources under Project Manager.


18. In the Add Sources window, select Add or Create design sources and click on Next.


19. Click on Add files and then provide the top.v file attached here.

Click on Finish.


20. Click on Add Sources under Project Manager.


21. Select Add or Create constraints and Click Next.


 22. Click on Add files and upload the top.xdc provided here, then click on Finish.


23. In Project Management Click on Generate bitstream.


24. You will see the following prompt:


Click on Yes.

A "Launch Runs" pop-up will appear. Click OK.

This will launch Synthesis followed by implementation, and generate the bitstream.

Our lab is now done.


XDC File Contents:

The XDC file contains the following:

create_clock -name clk_p -period 8 [get_ports clk_p]
set_property LOC G21 [get_ports clk_p]
set_property LOC AG14 [get_ports dout]

set_property IOSTANDARD LVCMOS18 [get_ports dout]
set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports clk_p]


Reason for use of IBUFDS:

The reason why we have used IBUFDS is that the board we have chosen requires a differential clock.

Each board will have its own specific pin LOCs and the System Clock frequencies that it can support.

This board can support 300Mhz and 125Mhz, so we are using 125Mhz and the Pin LOC which corresponds to it. The output is connected to an LED which is LOC'ed at AG14. The last 2 statements are used to specify the IOSTANDARD for the ports.