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Vivado Design Entry Chronicles - Mixed Design Entry

Xilinx Employee
Xilinx Employee
4 0 523

1. Launch Vivado.


2. Click on "New Project". Provide the project name and location as per your requirement.


3. Select "RTL Project" for the Project Type.


4. In the "Add Sources" window click Next. We will add sources later.

5. In the "Add Constraints"  window click Next. We will add constraints later.

6. In Part Selection, Select the "Boards" tab and select the Zynq UltraScale+ ZCU102 Evaluation Board.


7. The project should now be created with the name you have provided and the part you selected.


8. Click on "Create Block Design" under IP Integrator. Provide the design name and Click OK.


9. Now we will add IP from the Xilinx Repository and IP generated by HLS (for more information on HLS IP generation, see Lab 3 in this series).

10. Let's add the HLS Repository (provided with this lab) to the IP Repository. Click "Settings" then "Repository" under IP and then click "+" to provide the path of the Repository.


11. Provide the Directory path to the HLS IP. Click Select.


12. You will see confirmation that the Repository has been added and a list of all IP cores within it.

Review the details and click OK, then click OK on the "Settings" window.


13. In the Diagram window, click on the "+" symbol to add IP.


14. The IP Selection Window will open. Type 'count' in the Search box.

Select both IP cores and hit Enter.


15. Now you should see both IP cores (from HLS and from IP Integrator) in your block diagram.

16. The Binary Counter IP has a default size of 16. Let's increase it to 32. Double click on Binary Counter to customize it.

Change the Output Width value from 16 to 32. Click OK.


17. Check the width of Q for the Binary Counter. It should now be [31:0].

18. Because both IP will have same top clock, we will establish a connection for the clock pin of both IP cores. First we need set the CLK pin of the IP as an external port.

a) Left click to select the "CLK" pin of "Binary Counter". Once it is highlighted, right click on it and select "Make External".

This should create an external port for the CLK pin of the Binary Counter IP.


b) Select the "ap_clk" pin of the Count_toggle IP and drag it to the newly created external clock port. This should establish connections in the clock pins of both IP.


19. Now, let's set other pins of interest as external ports. Similarly to in step 18 above, make the "Q[31:0]" pin of the Binary Counter and the "toggle" pin of the Count_toggle IP external.

Your block diagram should look like the below example:



20. Now in the Sources Tab, right click design_1 and select "Create HDL Wrapper". This step generates an RTL wrapper for the block diagram. Click OK on any pop-up windows, and leave the default selection as-is.


21. You can double-click the generated HDL wrapper named "design_1_wrapper" to see its contents.


22. Until now we have added IPs from HLS and the Xilinx Vivado IP Repository. Let's add a counter via the RTL file and top level of the  design that instantiates the counter (RTL) and block diagram. 

Click on Add Sources, and in the dialog box which opens, select "Add or Create design sources" and click Next.


23. Click on "Add Files". Browse through the directory and add the files "rtl_counter.v" and "top.v" (provided with this lab).

Click OK and then Finish in the Add Sources window.


24. Similarly, add the constraints file "top.xdc" provided with this lab.


25. Allow a moment for Vivado to upgrade the design hierarchy, it should then appear as below.


26. Design setup is now complete.

Click on "Generate Bitstream". This will run synthesis, implementation, and generate the bitstream.


27. Observe the Design Runs and confirm that all runs have finished.


28. The output is connected to an LED which is LOC'ed at AG14.  This is done via XDC.

Our lab is now done.