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Vivado Design Entry Chronicles - RTL Design Entry

Xilinx Employee
Xilinx Employee
3 1 344

This blog entry is the first lab in a series which will be targeted at beginners in FPGA design entry using Vivado.

These labs are organized to give the user a quick start and help them to get a feel for how the tool flow works. We have picked a very simple design that is easy to understand so that different steps in the flow can be explained easily.

The labs will be presented in this order – RTL Flow, IP based Flow, HLS based Flow, IP Integrator based Flow, and then finally creating a design using a mix of the earlier flows.

This first lab is an RTL Flow.  Each step includes a screen shot for the user to refer to as they try it out.

Steps to follow:

1. Invoke Vivado.

N1.png

2. Provide the project name of your choice (project_1 is the default name that the tool uses) and the path where you want to create the project, then click Next.

N2.png

 

3. Select RTL Project (this option is selected by the tool by default), then click Next.

N3.png

4.You will get a prompt to Add Sources. Select Add Files and provide the attached RTL file (top.v).

Click Next.

image.png

Below are the details of the RTL:

image.png

The RTL describes a simple free-running 32 bit counter. Once the counter reaches its max value, a flip-flop is toggled. This flop is connected to the output.

A differential Buffer is used (IBUFDS) to connect a differential pair of clocks whose output is used in the design. We will see in the following section why this is being used.

 

5.You will see an Add Constraints dialog box with an Add Files option.

Select Add Files and provide the attached top.xdc, then click Next.

image.png

6. Click the boards tab and search for zcu102, then select the board that appears here (Zynq UltraScale+ ZCU102 Evaluation Board).

Click Next.

image.png

7. In the following window, click Finish.

8. On the Left hand side, you will see a "Generate Bitstream" button.

Click on this button.

image.png

9. You will get a prompt similar to the following:

n4.png

Click Yes. You will see one more pop up which asks to Launch the runs. Click OK.

This will trigger Synthesis followed by Implementation, and the bitstream will be generated.

Our lab is now done.

XDC File Contents:

The XDC file contains the following:

create_clock -name clk_p -period 8 [get_ports clk_p]
set_property LOC G21 [get_ports clk_p]
set_property LOC AG14 [get_ports dout]

set_property IOSTANDARD LVCMOS18 [get_ports dout]
set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports clk_p]

 

Reason for use of IBUFDS:

The reason why we have used IBUFDS is that the board we have chosen requires a differential clock.

Each board will have its own specific pin LOCs and the System Clock frequencies that it can support.

This board can support 300Mhz and 125Mhz, so we are using 125Mhz and the Pin LOC which corresponds to it. The output is connected to an LED which is LOC'ed at AG14. The last 2 statements are used to specify the IOSTANDARD for the ports.

 

1 Comment
Scholar dpaul24
Scholar

Hope newbies will find it useful.