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Vivado Timing Closure Techniques, Total Pulse Width Violation (TPWS) Part 1

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There are several types of timing violations that fall under the category of Pulse Width Violations.

    1.  Max Skew Violations (covered in this blog)
    2.  Min Period Violations (covered here).
    3. Max Period Violations
    4. Low Pulse Width Violations
    5. High Pulse Width Violations

The Pulse Width Violations are accounted for under the TPWS section of Report Timing Summary.

The worst of all of the Pulse Width violations are reported as the Worst Pulse Width Slack (WPWS).

Capture1.PNG

For in-depth information about the pulse width violations, open the pulse width violation report in the Vivado GUI ( Select Reports -> Timing -> Report Pulse Width) or through the following Tcl command:

report_pulse_width

 

Max Skew Violations:

This blog entry covers Max Skew Violations only. 

Examples of Max Skew Violations:

The screen capture below shows max skew violations with negative slack.

Capture2.PNG

In the above example, the Actual Max Skew value is the difference between the arrival time for CLK calculated at the Fast process corner in Max, and the arrival time for CLKDIV at the Fast process corner in Min.

You can check it in the timing report for a particular path type.

Note: timing should be reported in the same corner (Slow/Fast), but the 2 pins must be reported in Min/Max.

 

For a detailed explanation of how Required and Actual values get calculated, see (Xilinx Answer 72121).

 

Checklist to resolve Max skew violations:

 

  1. First, check the topology of the clock tree paths which are reported as failing paths.
    One of the clock paths will be referred to as the "Reference Path" and the other will have the skew above the specifications. 
     
  2. Check that you are using optimal clocking topologies. Users can check the DRC report and methodology report about messages on the issues of sub-optimal clocking topologies. (UG949)  "Clocking Topology recommendations" can be useful for understanding Xilinx recommended clocking topologies.

  3. Make sure that the clock buffers are placed inside the same clock region. The clock tree should also be balanced.
    It is best practice to avoid having the clock tree cross SLRs. 

  4. You can also add the CLOCK_DELAY_GROUP property to see if it can overcome this violation.
    See (Xilinx Answer 67885)  for more information.

  5. Please ensure that the clock root of the buffers driving the pins is assigned to the same clock region.
    To manually set the clock root value, the USER_CLOCK_ROOT constraint can be used.