Design and Debug Techniques Blog

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Design and Debug Techniques Blog

Moderator
Moderator

On certain occasions, for example while working remotely, it might be necessary to access a device that is not locally available.

This brief tutorial demonstrates how to share and access a board which is in a remote Lab location, or in the possession of a co-worker.

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Xilinx Employee
Xilinx Employee

The Xilinx PCI Express IP comes with the following integrated debugging features.

  • JTAG Debugger
  • Enable In-System IBERT
  • Descrambler in Gen3 Mode

The 'JTAG Debugger' provides the following information to assist in debugging PCI Express link training issues:

  • A graphical view of LTSSM states
  • A GUI based receiver detect status on all configured lanes
  • PHY RST state machine status

In-system IBERT provides the PCIe link Eye Diagram. The JTAG Debugger and the In-system IBERT features together provide instant information on the probable source of the link training issue.

Gen3 Mode Descrambler option provides a decoded interface of the PIPE data. It allows users to view the packets on the PCIe link. Details on this feature and how to decode the packet are available in this blog.

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Xilinx Employee
Xilinx Employee

This blog entry will show you how to create an AXI CDMA Linux userspace example application. The example design will transfer data from the PS DDR to the AXI BRAM through the AXI CDMA on a Zynq UltraScale+ RFSoC ZCU111 Evaluation Kit.

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Community Manager
Community Manager

Xilinx has a number of Online resources including Documentation, Answer Records, a Wiki, and the forums you are reading this blog entry on.

Which resource you should check first depends on the type of design you are working on and what stage of the design you are at.

This blog entry contains information on each of these resources and the best time to use them.

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Moderator
Moderator

This blog entry is intended to get you started with running Ethernet applications on our Xilinx® Versal™ ACAP VCK190 Evaluation Kit. It provides design creation steps for using the 2019.2 version of Vivado and Vitis to build and run Ethernet applications on a VCK190 board.

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Xilinx Employee
Xilinx Employee

This blog provides a list of videos showcasing the tutorials in (UG1209). The videos have been created using Vivado® Design Suite version 2019.1 and the Xilinx Software Development Kit (SDK). The examples are targeted for the Zynq® UltraScale+™ MPSoC ZCU102 Rev1 Evaluation Board.

Video 1 shows how to run an application using the ZCU102 board. While most of the videos run the applications using QEMU, the applications can also be run on the ZCU102 by following Video 1.

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Xilinx Employee
Xilinx Employee

This blog entry touches on how solving methodology issues will help you to make more effective timing closure decisions.

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Moderator
Moderator

If you are running the RF Data Converter IP simulation, you might have seen that it comes with its own simulation testbench.

This testbench can seem a little daunting. When trying to understand what is going on, there are many source files and it may not be clear where to even start. 

This Blog entry gives you a guide to how the IP example simulation can be used to check out the RF Data Converter. 

We'll  show you what the most important parts of the testbench are and how it is built ,and we'll also step through how it works.

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Xilinx Employee
Xilinx Employee

This blog entry provides a step by step video and links to associated documents with instructions for installing and running the QDMA Linux Kernel driver. It also provides some debug information.

It should be used in conjunction with the ‘read me’ file and documentation that comes with the driver. The QDMA Linux Kernel Driver can be downloaded from the link below:

https://github.com/Xilinx/dma_ip_drivers/tree/master/QDMA/linux-kernel

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Xilinx Employee
Xilinx Employee

XAPP1247 is an example application for Multiboot and Fallback when using Barrier Images. This Quick blog entry covers a method to test the barrier timer flow and an issue that can arise when doing so.

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Moderator
Moderator

In this new entry part of the AXI Basics series we look at how we can create an AXI Sniffer IP which can be used in Xilinx Vivado IP Integrator.

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Moderator
Moderator

In this fouth entry in the the AXI Basic Series, we will see an example of how to use the AXI protocol checker feature of the Xilinx AXI Verification IP (AXI VIP)

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Moderator
Moderator

This entry in the AXI Basics Series shows how the Xilinx AXI Verification IP can be used to simulate an AXI4-Lite master interface. We also look in detail at AXI4-Lite Read/Write transactions.

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Moderator
Moderator

I2C is a serial protocol for two-wire interface to connect low-speed devices like EEPROMs, Sensors, RTC, ADC/DAC, and other compatible I/O interfaces in embedded systems. 

In this article, you will learn about the basics of Inter-Integrated Circuit (I2C or IIC) and usage of this protocol bus for short distance communcation.

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Moderator
Moderator

The Vivado Integrated Design Environment supports Universal Verification Methodology (UVM) when using Vivado Simulator.

This blog entry covers the steps to create a UVM example design in Vivado.

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Moderator
Moderator

Modern RF signal chains demand extremely high data converter performance across multiple channels. This means that for Xilinx RF Data Converters a key requirement is to have synchronization across multiple ADC/DAC tiles, RFSoC devices and even boards. 

Find out how Xilinx provides the solution to the Multi-Tile Synchronization problem to enable Beamforming, Massive MIMO and Phased Array Radar

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Moderator
Moderator

This blog entry covers the basics of configuring the device tree to add the details of external peripherals and third-party applications to a PetaLinux project.

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Moderator
Moderator

eFUSE is one-time programmable which means once the FUSE is blown with a particular key it can never be programmed with other keys.

In this article we will discuss some of the AES key verification steps you should follow before programming the eFUSE key physically on the device.

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Moderator
Moderator

This entry in the AXI Basics Series introduces the Xilinx AXI Verification IP, which can be used to simulate AXI interfaces.

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Moderator
Moderator

AXI is a processor interface widely used in designs on Xilinx devices. This new series will cover some of the basics about the AXI interface.

This first article in the series gives an overview of the AXI standard.

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Moderator
Moderator

Are you a Xilinx Software Development Kit (SDK) user?

Are you planning to migrate your project to the Vitis Software Platform?

Then here is a step by step guide for project migration.

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Xilinx Employee
Xilinx Employee

This blog entry focuses on scenarios involving multiple drivers, how Vivado Synthesis handles such scenarios, and how it reports on them.

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Moderator
Moderator

Do you want to learn how to debug issues quickly for your Video Application? In this Video Series entry, the debugging secrets of the Xilinx Technical Support team are shared with the community.

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Xilinx Employee
Xilinx Employee

A lot of FPGA designs can struggle to hit their required performance targets. The reasons for this are varied but here is a list of some possible causes:

  • Not following the UltraFast Design Methodology
  • Poor timing constraints
  • Over utilization
  • Too many control sets
  • Sub-optimal clocking
  • High number of logic levels for target performance
  • Bad floorplans
  • Routing congestion
  • Tool optimization limited due to constraints

In this blog find out how 'report_qor_suggestions' can enhance your productivity by automating solutions to problems that limit FPGA performance.

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Moderator
Moderator

In this new entry part of the Xilinx Video Series, we will have a look at the Video Frame Buffer IP and its example design in Vivado and Vitis 2019.2.

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Moderator
Moderator

When you encounter a licensing issue in Vivado/ISE, what should you do next?

This blog entry covers how to debug licensing related issues.

It is broken up into four sections:

  • Floating license related issues
  • Node-Locked license related issue
  • Dongle Related licensing information and known issues
  • IP Core license related issues
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Moderator
Moderator

The Video example designs are great platforms for showcasing a working design and for providing a fast way to test your design in hardware.

However, example designs are only tested on the platform that they are released for, they are not portable by default, and there is no guaranteed automated way to port a design.  

What do you do when you want to design for a platform that does not have an example design?

In this blog, I will outline the steps to port an example design targeting the VCU118 board to the VCU128. The steps outlined here are not the only way that this can be done, but they are the most effective way that I know.

If you have other tips or tricks, please comment at the end of this post.

Required Hardware: VCU128 development board and TB-FMCH-HDMI4K FMC card.

 

 

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Xilinx Employee
Xilinx Employee

One of the new data types in SystemVerilog is the union.

A union allows you to refer to a single section of data in different ways.

This article will talk about how to use unions and how the synthesis tool deals with them.

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Moderator
Moderator

Welcome to the Vivado Timing Closure Techniques series.

In this series we will cover a number of types of timing violations that fall under the category of Pulse Width Violations.

This blog entry covers Max Skew Violations.

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Moderator
Moderator

Welcome to the Vivado Timing Closure Techniques series.

In this series we will cover a number of types of timing violations that fall under the category of Pulse Width Violations.

This blog entry covers Min Period Violations.

 

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