The Xilinx PCI Express IP comes with the following integrated debugging features.
Enable In-System IBERT
Descrambler in Gen3 Mode
The 'JTAG Debugger' provides the following information to assist in debugging PCI Express link training issues:
A graphical view of LTSSM states
A GUI based receiver detect status on all configured lanes
PHY RST state machine status
In-system IBERT provides the PCIe link Eye Diagram. The JTAG Debugger and the In-system IBERT features together provide instant information on the probable source of the link training issue.
Gen3 Mode Descrambler option provides a decoded interface of the PIPE data. It allows users to view the packets on the PCIe link. Details on this feature and how to decode the packet are available in this blog.
This blog entry will show you how to create an AXI CDMA Linux userspace example application. The example design will transfer data from the PS DDR to the AXI BRAM through the AXI CDMA on a Zynq UltraScale+ RFSoC ZCU111 Evaluation Kit.
This blog entry is intended to get you started with running Ethernet applications on our Xilinx® Versal™ ACAP VCK190 Evaluation Kit. It provides design creation steps for using the 2019.2 version of Vivado and Vitis to build and run Ethernet applications on a VCK190 board.
This blog provides a list of videos showcasing the tutorials in (UG1209). The videos have been created using Vivado® Design Suite version 2019.1 and the Xilinx Software Development Kit (SDK). The examples are targeted for the Zynq® UltraScale+™ MPSoC ZCU102 Rev1 Evaluation Board.
Video 1 shows how to run an application using the ZCU102 board. While most of the videos run the applications using QEMU, the applications can also be run on the ZCU102 by following Video 1.
Modern RF signal chains demand extremely high data converter performance across multiple channels. This means that for Xilinx RF Data Converters a key requirement is to have synchronization across multiple ADC/DAC tiles, RFSoC devices and even boards.
Find out how Xilinx provides the solution to the Multi-Tile Synchronization problem to enable Beamforming, Massive MIMO and Phased Array Radar
The Video example designs are great platforms for showcasing a working design and for providing a fast way to test your design in hardware.
However, example designs are only tested on the platform that they are released for, they are not portable by default, and there is no guaranteed automated way to port a design.
What do you do when you want to design for a platform that does not have an example design?
In this blog, I will outline the steps to port an example design targeting the VCU118 board to the VCU128. The steps outlined here are not the only way that this can be done, but they are the most effective way that I know.
If you have other tips or tricks, please comment at the end of this post.
Required Hardware: VCU128 development board and TB-FMCH-HDMI4K FMC card.