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Design and Debug Techniques Blog

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Design and Debug Techniques Blog

Moderator
Moderator

 

The AXI Video Direct Memory Access (VDMA) IP allows a video stream from an AXI4-Stream interface to be moved to a memory. In this video series entry, we will show how to easily add the AXI VMDA IP in a video pipeline.

 

 

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Community Manager
Community Manager

Hello and welcome to part one of the hardware simulation blog series.

In this series we will review and explore the various Signal Integrity (SI) issues that affect today’s High-Speed Printed Circuit Board (PCB) designs and how to avoid them using simulation.

In this first entry we will look at the various models available for SI simulation, the differences between them, and which are preferrable when running an SI simulation.

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Moderator
Moderator

In this video series entry, we will create a design (Vivado design + SDK application) to generate a video output on the HDMI output connector of a PYNQ™-Z2 board.

This entry is a continuation of the Video Series from the Video board. You can see all previous entries in the Video series here.

 

 

 

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Xilinx Employee
Xilinx Employee

As frequency requirements continue to increase in complex FPGA designs, breaking the huge combinational logic and finding the optimal point for pipeline register insertion becomes more difficult. 

Register retiming techniques come in very useful in these situations.  This article will go into detail on the retiming feature within Vivado Synthesis.

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Moderator
Moderator

Welcome to the Xilinx Design and Debug Techniques blog, a new weekly blog where our Applications Engineers share their experiences and lessons learned designing and debugging with Xilinx.

This first entry is a continuation of the Video Series from the Video board. You can see all previous entries in the Video series here.

The Video Series will be published here from now on, along with entries from other Xilinx Engineers on their areas of expertise.

In the previous Video Series entry (Number 21), we created a design which sends a pattern (using the Test Pattern Generator (TPG) core) to the on-board HDMI of a Zynq®-7000 SoC ZC702 Evaluation Kit.

However, for this application, the resolution was fixed to 800x600p in the hardware design (there was no option to change it in the application).

In this Video Series entry we will see how to modify the hardware design and the application to support multiple video resolutions.

 

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