Design and Debug Techniques Blog

cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 

Design and Debug Techniques Blog

Moderator
Moderator

In AXI Basics 6 - Introduction to AXI4-Lite in Vitis HLS, we learned how to create an IP in HLS with an AXI4-Lite interface using C code. In this blog, we will learn how to export our IP so that we can use it in the Vivado Design Suite, and how to connect it to other IP cores and a processor.

Read more...

more
2 0 136
Moderator
Moderator

Want to create your own IP with an AXI4-Lite interface, but unsure how to get started? This article will teach you the basics of how to create an AXI4-Lite interface in Vitis HLS using C code. 

Read more...

more
9 0 1,030
Moderator
Moderator

In this new entry part of the AXI Basics series we look at how we can create an AXI Sniffer IP which can be used in Xilinx Vivado IP Integrator.

Read more...

more
3 2 2,690
Moderator
Moderator

In this fouth entry in the the AXI Basic Series, we will see an example of how to use the AXI protocol checker feature of the Xilinx AXI Verification IP (AXI VIP)

Read more...

more
1 0 2,057
Moderator
Moderator

This entry in the AXI Basics Series shows how the Xilinx AXI Verification IP can be used to simulate an AXI4-Lite master interface. We also look in detail at AXI4-Lite Read/Write transactions.

Read more...

more
5 4 3,633
Moderator
Moderator

This entry in the AXI Basics Series introduces the Xilinx AXI Verification IP, which can be used to simulate AXI interfaces.

Read more...

more
8 9 7,042
Moderator
Moderator

AXI is a processor interface widely used in designs on Xilinx devices. This new series will cover some of the basics about the AXI interface.

This first article in the series gives an overview of the AXI standard.

Read more...

more
16 2 10.3K