In previous video series entries, I discussed the common color spaces for Image and Video; RGB (Video Series 2), YCbCr4:4:4 (Video Series 9) and YCbCr4:2:2/YCbCr4:2:0 (Video Series 10).

The Video Processing Subsystem IP includes a Color Space Converter (CSC) sub-core which allows you to convert a video stream from one of these color spaces to any of the others.

In this Video Series entry, we will see how to add the VPSS IP configured as a Color Space Converter Only.

The Video Processing Subsystem IP is an IP included for free in Vivado which supports multiple video processing features as Deinterlacing, Video Scaling (up and down scaling), Color Space Conversion, and Frame Rate.

This entry of the Video Series contains advice from Florent on how to start designing with this IP.

The Xilinx Video Series covers a series of topics which help you learn how to use Xilinx Video IPs, as well as how to debug potential issues.

In this entry, Video Series number 26, we will see how the AXI Video Direct Memory Access (VDMA) IP can be used for applications such as video crop, picture in picture, or a soft pattern generator.

The Xilinx Video Series covers a series of topics which help you learn how to use Xilinx Video IPs, as well as how to debug potential issues.

This entry, the 25th of the series, shows how to read the VDMA IPs status registers using the Xilinx Software Command Line Tool (XSCT) console in SDK, in order to detect possible root causes for errors happening with the AXI VDMA IP.

The AXI Video Direct Memory Access (VDMA) IP allows a video stream from an AXI4-Stream interface to be moved to a memory. In this video series entry, we will show how to easily add the AXI VMDA IP in a video pipeline.

In this video series entry, we will create a design (Vivado design + SDK application) to generate a video output on the HDMI output connector of a PYNQ™-Z2 board.

This entry is a continuation of the Video Series from the Video board. You can see all previous entries in the Video series here.

Welcome to the Xilinx Design and Debug Techniques blog, a new weekly blog where our Applications Engineers share their experiences and lessons learned designing and debugging with Xilinx.

This first entry is a continuation of the Video Series from the Video board. You can see all previous entries in the Video series here.

The Video Series will be published here from now on, along with entries from other Xilinx Engineers on their areas of expertise.

In the previous Video Series entry (Number 21), we created a design which sends a pattern (using the Test Pattern Generator (TPG) core) to the on-board HDMI of a Zynq®-7000 SoC ZC702 Evaluation Kit.

However, for this application, the resolution was fixed to 800x600p in the hardware design (there was no option to change it in the application).

In this Video Series entry we will see how to modify the hardware design and the application to support multiple video resolutions.