Video Series 33 is a continuation of Video Series 32. In this Video Series, we will walk through the steps needed to create and update the Video Mixer example design application so that it can be output through the ZCU702 board 's On-Board HDMI.
This video Series entry shows an example of the Hardware Design which can use the On-Board HDMI output of the Zynq®-7000 SoC ZC702 evaluation kit using the ADV7511 to visualize the Video Mixer example design.
The Video Mixer example design is originally described in Chapter 5 of (PG243).
Note: the design will need a software application to work. This will be done in the following Video Series entry (Number 33). This series also has a prerequisite of Video Series 19 and Video Series 20, which describe the ADV7511.
The Video Processing Subsystem IP is an IP included for free in Vivado which supports multiple video processing features as Deinterlacing, Video Scaling (up and down scaling), Color Space Conversion, and Frame Rate.
This entry of the Video Series contains advice from Florent on how to start designing with this IP.
The Xilinx Video Series covers a series of topics which help you learn how to use Xilinx Video IPs, as well as how to debug potential issues.
This entry, the 25th of the series, shows how to read the VDMA IPs status registers using the Xilinx Software Command Line Tool (XSCT) console in SDK, in order to detect possible root causes for errors happening with the AXI VDMA IP.
The AXI Video Direct Memory Access (VDMA) IP allows a video stream from an AXI4-Stream interface to be moved to a memory. In this video series entry, we will show how to easily add the AXI VMDA IP in a video pipeline.