03-13-2018 07:03 AM
For our project, we have a Microblaze in a Kintex 7 custom design board. The design also include an AXI DDR3 interface. The bitstream in generated in Vivado 2017.3 and the hardware is exported to SDK as system.hdf and system.bit files.
In SDK, we have wrote our application, which is quite large and doesn't fit in the BRAM of the Microblaze. We are able to program the fpga with the bootloop.elf and system.bit file and are able to debug it on the hardware platform.
We know want to create a unique .bit file which contains our fpga bitstream, the bootloop.elf and the appli.elf files in order to configure the FPGA and loat the content of the Microblaze at startup. We don't have any flash, the .bit file is dumped from a PC, goes through an FX3 device and is pushed via Select SlaveMAP method to the FPGA.
Updatemem tool seems a good choice but it failed each time because the memory range is not correct (0x80000000:0x8001718B) according to the definition in the MMI file.
How can we create our .bit file ?
03-13-2018 07:06 AM
03-13-2018 07:14 AM
@hbucher, Bootgen seems to be usable only for Zynq based SOC, we only have a Kintex 7 FPGA. The output format is a BIF file not a .BIT file. What is the meaning of FSBL ?
03-13-2018 07:16 AM - edited 03-13-2018 07:31 AM
@c.fauvel FSBL = first stage boot loader.
It is the ELF that is responsible for copying the executables in the boot media and placing them in the target memory.
Bootgen creates .BIT files.
03-21-2018 01:43 PM