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678 Views
Registered: ‎09-30-2011

Sample Device Tree for Zynq7000 QSPI dual-stacked 4 bit configuration

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I am having some trouble getting access to both QSPI devices in a dual-stack 4 bit configuration. I am almost 100% certain my device tree is wrong but I can't figure out why.

 

Here is what I have:

 

qspi: qspi@e000d000 {

compatible = "xlnx,zynq-qspi-1.0";

clock-names = "ref_clk", "pclk";

clocks = <&clkc 10>, <&clkc 43>;

interrupt-parent = <&ps7_scugic_0>;

interrupts = <0 19 4>;

is-dual = <0>;

/* is stacked set to 1 because that's what we need */

is-stacked = <1>;

/* I assume that stating that 2 chip selects are used is required and necessary */

num-cs = <2>;

reg = <0xe000d000 0x1000>;

 

/* the documentation says this does nothing */

xlnx,qspi-mode = <0x2>;

#address-cells = <1>;

#size-cells = <0>;

/* this shows up as is in the first flash device */

flash@0 {

    compatible = "n25q128";

    reg = <0x0>;

    spi-tx-bus-width = <1>;

    spi-rx-bus-width = <4>;

    spi-max-frequency = <50000000>;

    #address-cells = <1>;

    #size-cells = <1>;

    partition@stuff {

        label = "stuff";

        reg = <0x0 0x100000>;

    };

/* I'm hoping this will be the second flash device */

flash@1 {

    compatible = "n25q128";

    reg = <0x100000>;

    spi-tx-bus-width = <1>;

    spi-rx-bus-width = <4>;

    spi-max-frequency = <50000000>;

    #address-cells = <1>;

    #size-cells = <1>;

    partition@more_stuff {

        label = "more_stuff";

        reg = <0x100000 0x100000>;

    };

 };

};

 

When I do an mtd access, I only get the first partition and is says it gets a JEDEC ID of 0 0 0 for the second one

 

How did I screw up?

 

Thanks for your help

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1 Solution

Accepted Solutions
604 Views
Registered: ‎09-30-2011

Re: Sample Device Tree for Zynq7000 QSPI dual-stacked 4 bit configuration

Jump to solution

OK. I found out the complete and correct answer. First off, Zynq and Zynq-MP are different. What I am going to describe is correct for Zynq and not Zynq-MP. Most of this information is written either in the Wiki, the documentation or the TRM but it is a bit here and a bit there with some contradicting verbiage along the way.

 

First off, in Vivado make sure that you define the QSPI interface on the PS side as Dual-Stacked 4 bit. That sets up the controller to operate in that mode.

All the rest is software related.

  • The kernel must be built with CONFIG_SPI_ZYNQ_QSPI_DUAL_STACKED set
  • The device tree is-stacked value is not used and should not be specified in the specification
  • The device tree num-cs value should be 1 (not 2 even though 2 CS pins are used)
  • The device tree does not need to specify the two devices with independent CS pins separately within the QSPI controller definition, rather they must be specified as a single device with a single CS
  • Although the documentation suggests otherwise (sometimes), for Zynq the 2 PROMs must be the same size and family

Here is a sample device tree:

&qspi {
    /*
*      For zynq-qspi you do not need to mention the property “is-stacked” instead you need
*      to enable CONFIG_SPI_ZYNQ_QSPI_DUAL_STACKED
*      in the kernel, also stacked mode is the controller feature so “num-cs = <1>;“ is all that is needed
    */
compatible = "xlnx,zynq-qspi-1.0";
is-dual = <0>;
num-cs = <1>;
/* the documentation says this is unused */
xlnx,qspi-mode = <0x2>;
status = "okay";
clock-names = "ref_clk", "pclk";
clocks = <&clkc 10>, <&clkc 43>;
interrupt-parent = <&intc>;
interrupts = <0 19 4>;
reg = <0xe000d000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
/*
* the stacked configuration appears as a single memory
* specification here and is not divided into upper
* and lower flash blocks

* We are using two 256Mbit PROMs which affords us

* (256Mbit * 2)/8 bits/byte = 64MBytes of memory
*/
spi_flash@0 {
compatible = "n25q256a", "jedec,spi-nor";

/* only one CS so set reg to 0 */

reg = <0x0>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <4>;
spi-max-frequency = <50000000>;
#address-cells = <1>;
#size-cells = <1>;

/****
* partitions lifted from OPAT device tree
****/
partition@uboot_spl {
label = "uboot_spl 0x00000000";
reg = <0x00000000 0x000E0000>;
};
partition@uboot_env {
label = "uboot_env 0x000E0000";
reg = <0x000E0000 0x00020000>;
};
partition@uboot {
label = "uboot 0x00100000";
reg = <0x00100000 0x500000>;
}; partition@persistent {
label = "persistent 0x03AB4000";
reg = <0x03AB4000 0x0054C000>;
};
};
};

 

3 Replies
Xilinx Employee
Xilinx Employee
650 Views
Registered: ‎06-27-2017

Re: Sample Device Tree for Zynq7000 QSPI dual-stacked 4 bit configuration

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Hi neil@formidableengineeringconsultants.com,

 

Below is the sample device tree for QSPI flash along with controller,

clock-names = "ref_clk", "pclk";
clocks = <0x1 0xa 0x1 0x2b>;
compatible = "xlnx,zynq-qspi-1.0";
status = "okay";
interrupt-parent = <0x4>;
interrupts = <0x0 0x13 0x4>;
reg = <0xe000d000 0x1000>;
#address-cells = <0x1>;
#size-cells = <0x0>;
u-boot,dm-pre-reloc;
is-dual = <0x0>;
num-cs = <0x1>;
spi-rx-bus-width = <0x4>;
spi-tx-bus-width = <0x4>;

flash@0 {
compatible = "n25q512a", "micron,m25p80";
reg = <0x0>;
spi-tx-bus-width = <0x1>;
spi-rx-bus-width = <0x4>;
spi-max-frequency = <0x2faf080>;
#address-cells = <0x1>;
#size-cells = <0x1>;

 

Please keep compatible name as "compatible = "n25q512a", "micron,m25p80"; so that qspi driver will invoke and will try to detect the flash using jedec codes. you can check the flash support is avaialable or not in UG908 guide

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_1/ug908-vivado-programming-debugging.pdf

 

Regards
Kranthi
--------------------------
Don't forget to reply, kudo, and accept as solution.

Best Regards
Kranthi
--------------------------
Don't forget to reply, kudo, and accept as solution.
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633 Views
Registered: ‎09-30-2011

Re: Sample Device Tree for Zynq7000 QSPI dual-stacked 4 bit configuration

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Hi @gudishak,

 

I am specifically asking for a sample device tree that maps to a dual-stacked 4 bit QSPI setup. I believe what you have posted does not fulfil that. It also looks incomplete syntactically.

 

Thanks for the pointer to the supported PROM list.

0 Kudos
605 Views
Registered: ‎09-30-2011

Re: Sample Device Tree for Zynq7000 QSPI dual-stacked 4 bit configuration

Jump to solution

OK. I found out the complete and correct answer. First off, Zynq and Zynq-MP are different. What I am going to describe is correct for Zynq and not Zynq-MP. Most of this information is written either in the Wiki, the documentation or the TRM but it is a bit here and a bit there with some contradicting verbiage along the way.

 

First off, in Vivado make sure that you define the QSPI interface on the PS side as Dual-Stacked 4 bit. That sets up the controller to operate in that mode.

All the rest is software related.

  • The kernel must be built with CONFIG_SPI_ZYNQ_QSPI_DUAL_STACKED set
  • The device tree is-stacked value is not used and should not be specified in the specification
  • The device tree num-cs value should be 1 (not 2 even though 2 CS pins are used)
  • The device tree does not need to specify the two devices with independent CS pins separately within the QSPI controller definition, rather they must be specified as a single device with a single CS
  • Although the documentation suggests otherwise (sometimes), for Zynq the 2 PROMs must be the same size and family

Here is a sample device tree:

&qspi {
    /*
*      For zynq-qspi you do not need to mention the property “is-stacked” instead you need
*      to enable CONFIG_SPI_ZYNQ_QSPI_DUAL_STACKED
*      in the kernel, also stacked mode is the controller feature so “num-cs = <1>;“ is all that is needed
    */
compatible = "xlnx,zynq-qspi-1.0";
is-dual = <0>;
num-cs = <1>;
/* the documentation says this is unused */
xlnx,qspi-mode = <0x2>;
status = "okay";
clock-names = "ref_clk", "pclk";
clocks = <&clkc 10>, <&clkc 43>;
interrupt-parent = <&intc>;
interrupts = <0 19 4>;
reg = <0xe000d000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
/*
* the stacked configuration appears as a single memory
* specification here and is not divided into upper
* and lower flash blocks

* We are using two 256Mbit PROMs which affords us

* (256Mbit * 2)/8 bits/byte = 64MBytes of memory
*/
spi_flash@0 {
compatible = "n25q256a", "jedec,spi-nor";

/* only one CS so set reg to 0 */

reg = <0x0>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <4>;
spi-max-frequency = <50000000>;
#address-cells = <1>;
#size-cells = <1>;

/****
* partitions lifted from OPAT device tree
****/
partition@uboot_spl {
label = "uboot_spl 0x00000000";
reg = <0x00000000 0x000E0000>;
};
partition@uboot_env {
label = "uboot_env 0x000E0000";
reg = <0x000E0000 0x00020000>;
};
partition@uboot {
label = "uboot 0x00100000";
reg = <0x00100000 0x500000>;
}; partition@persistent {
label = "persistent 0x03AB4000";
reg = <0x03AB4000 0x0054C000>;
};
};
};