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Observer gosha-z
Observer
95 Views
Registered: ‎09-07-2018

ZynqMP SERDER error

Introduction: ZynqMP ZU3CG, GEM0 attached to GT Lane0, Reference source: RefClk0, RefClk0 clock derived from Silabs Si5344 generator.When I turn on GEM0, rebuild PMU firmware and FSBL with _DEBUG_DETAILED then trying to start system by JTAG download, I get the following messages on console:

XFSBL_PSU_INIT_FAILED
================= In Stage Err ============
Fsbl Error Status: 0x0#SERDES initialization timed out
XFSBXL_PPFSUW_:IN ICT_aFlAIlLiEDn
 =R==O=M== =P==W=R==D=N== =H=and Sta.Donr
============
Fsbl Error Status: 0x0

What does it mean? Do I miss something?

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3 Replies
Moderator
Moderator
62 Views
Registered: ‎03-19-2014

Re: ZynqMP SERDER error

This message means your SERDES did not initialize correctly.    In psu_init the code loops waiting for the SERDES to initialize, if that does not happen in a prescribed time, the code times out.      Review your design.  

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Observer gosha-z
Observer
53 Views
Registered: ‎09-07-2018

Re: ZynqMP SERDER error

Does it mean that valid clock signal must be available on RefClk pins before psu-init run?

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Moderator
Moderator
44 Views
Registered: ‎03-19-2014

Re: ZynqMP SERDER error

Yes.

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