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mbssch
Contributor
Contributor
8,008 Views
Registered: ‎03-20-2008

10.1 SP2 brings upper limit for C_NUM_SLAVES in plb_v46

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Hallo there,

 

after upgrading EDK to SP2 I get the following error while generating the netlist for my processor:

 

ERROR:MDT -
   C:\Xilinx\10.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_03_a\data\plb_v4
   6_v2_1_0.mpd line 35 - PARAMETER C_PLBV46_NUM_SLAVES has value 19 which does
   not fall in the range (1:16), specified in MP

 

Actually I do have 19 slaves, but that never was a problem before. In the change log for plb I found the line: "Add MPD range attributes for C_NUM_MASTERS and C_NUM_SLAVES."

 

After manually changing the range from 1:16 to 1:32 in the MPD file, everything works fine again.

 

Is it really necessary to limit the number of plb slaves to such a low number? And what is the official way to overcome the problem, a second plb bus?

 

Greetings

Stefan Schwarzer

 

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xiaofeip
Xilinx Employee
Xilinx Employee
9,472 Views
Registered: ‎08-07-2007

Hi Stefan,

 

Not sure about the story behind the 16-slave limitation. But I assume that it'll be fine to give it a larger number as long as there's no timing problem.

 

-XF

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xiaofeip
Xilinx Employee
Xilinx Employee
9,473 Views
Registered: ‎08-07-2007

Hi Stefan,

 

Not sure about the story behind the 16-slave limitation. But I assume that it'll be fine to give it a larger number as long as there's no timing problem.

 

-XF

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akleica
Explorer
Explorer
6,897 Views
Registered: ‎11-13-2007
I just ran into this today with the 17th slave added. I too would like an 'official' answer from Xilinx about this.
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akleica
Explorer
Explorer
6,894 Views
Registered: ‎11-13-2007

And why does the tool open a blank file when I click on the link below? (It generates this link)

I know why, because it wraps the line and generates the incorrect link. Why can't they fix this? Hasn't anyone ever reported it before?

 

Performing System level DRCs on properties...
ERROR:MDT -
   C:\Xilinx\10.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_03_a\data\plb_v4
   6_v2_1_0.mpd line 35 - PARAMETER C_PLBV46_NUM_SLAVES has value 17 which does
   not fall in the range (1:16), specified in MPD

Running DRC Tcl procedures for OPTION SYSLEVEL_DRC_PROC...
ERROR:MDT - platgen failed with errors!
make: *** [implementation/system.bmm] Error 2
Done!

 

Why is the range limited to 16?

And finally, why does the MPD file have the number set to 8?

 

PARAMETER C_PLBV46_NUM_SLAVES = 8, DT = integer, RANGE = (1:16)

 

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mbssch
Contributor
Contributor
6,875 Views
Registered: ‎03-20-2008
I guess 8 is the default value. Meanwhile I ended up having a total of 25 slaves and everything still works fine. But you're right, an official statement would be nice.
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xtracool_protik
Visitor
Visitor
4,977 Views
Registered: ‎04-02-2010

hey guys what does it mean when it says ".../../../plb_v46_v2_1_0.mpd has value 0 which does not fall in range (1:16), specified in MPD "

 

This is my second project (trying to learn through few tutorials) on xilinx Virtex Pro-II and I was trying to put DIP, push button and LED (trying to display DIP status on LED).

However there was probably not a chance to put them all on plb0 (serial was there as well)

 

 

So I tried going by default way which gave me some error about plb_v46_0

 

So I tried assigning addresses only 32k apart for led, DIP and push button on plb0 only that didn't go well as well (thats when I got the above error)

 

Finally I removed push button all together and assigned 64k addresses to remaining 2  that wasn't of any help as well 

tried cleaning project but just not working

 

I just turned to FPGA programming not sure where to look for resources yet, sorry if this is really a stupid error

 

Thanks 

 

 

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xiaofeip_dup
Xilinx Employee
Xilinx Employee
4,939 Views
Registered: ‎08-07-2007

Hi Guys,

 

Not an official statement, but it's what I heard.

 

8 slaves on PLB bus are fully tested and 16 are lightly tested.   Any numbers more than that are not tested, but it doesn't mean that it wont' work.

 

Also, in latest verion of PLB (11.x that I checked), the error has been changed to a warning so that you can continue to implement your design.

 

-Felix

 

 

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