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179 Views
Registered: ‎08-28-2019

2016.2 Debugging C++ application

I have an existing C++ application which was developed in Xilinix 2016.2.  The build in 2016.2 downloads and runs ok and there is an FPGA application that shares a memory location with this application, this was configured using Vivado and all works ok.

 

There are a few issues with the application, however I cannot launch the debugger, for some reason the Debug button is always grayed and I have no idea what I haven't down.

 

I also have the 2019.1 version of Xilinx installed and using this IDE I can build and debug the application and the source is available, however for the 2019 build Vivado has not been run and it cannot access the shared memory with the FPGA, this results in a crash.

 

I would like to know either how to configure Vivado correctly so I can use 2019.1 to develop and debug or...how to configure the debugger correctly for 2016.2 so I can debug it?

Kind Regards,
Sy
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Moderator
Moderator
126 Views
Registered: ‎10-06-2016

Re: 2016.2 Debugging C++ application

Hi simon.platten@buhlergroup.com 

What do you mean that the debug button is always grayed? could you maybe provide a screenshot? SDK should allow you always to create a new debug configuration regardless of your projects in the workspace (Run + Debug Configurations).

For 2019.1 release what do you mean that ivado has not been run?? Do you mean that you are using the HDF file from 2016.1 release? What do you mean with how to configure Vivado correctly? Do you mean how to create a design in Vivado?

Regards


Ibai
Don’t forget to reply, kudo, and accept as solution.
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122 Views
Registered: ‎08-28-2019

Re: 2016.2 Debugging C++ application

Unfortunatety this after noon I pased on the hardware to a colleague to investigate.  All I can tell you is that the debug button is indeed grayed out.

In terms of Vivado, 2016.2 configuration exists but this doesn't work or is not used with SDK 2019.1.  I am not experienced with using Vivado and there is no documentation for the existing design that was implemented on 2016.2, the lack of documentation is not an issue for Xilinx or Vivado, its a company problem here....just doesn't help me to design or implement a solution.

Kind Regards,
Sy
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