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Participant doc
Participant
12,046 Views
Registered: ‎03-06-2008

ACE FILE PROBLEM

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HI EVERYBODY,

Iam working on the Virtex5 ML505 Board and iam using the system ACE module to configure my FPGA,

the problem is that the ace file of my application is generated but when i tried to run it on the board it doesn't work

 

so i want to ask about the bootloop is this file is necessary?

thanks, 

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Highlighted
11,196 Views
Registered: ‎10-12-2009

Re: ACE FILE PROBLEM

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Previously I used Xilinx EDK 11.2.

When update to the 11.3 problem was solved. 

genace.tcl from 11.2 have some bags.

 

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Xilinx Employee
Xilinx Employee
12,026 Views
Registered: ‎08-01-2007

Re: ACE FILE PROBLEM

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doc,

 

You can think of configuration through system ACE as an automated way of downloading the bitstream, connecting to the processor and then downloading the .ELF. If you want to connect to the processor, it must have atleast the bootloop running on it to come out of reset. Hence it is advisable to use the bitstream which has been initialized with the bootloop to generate the .ACE.

 

Hope this helps...

 

 

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Participant doc
Participant
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Registered: ‎03-06-2008

Re: ACE FILE PROBLEM

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i don't understand what's wrong with this ace file,i tried all the sollution but it doesn't work.

 

the bitstream is ok,the download.bit is ok

 

i tried to work with bootloop.elf and the slide_show.elf the result is the same (nothing). 

 

the ace file is generated but it doesn't work, if you have any suggestions ? please tel me. 

 

 

 

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Participant doc
Participant
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Registered: ‎03-06-2008

Re: ACE FILE PROBLEM iam sorry its not solved

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i don't understand what's wrong with this ace file,i tried all the sollution but it doesn't work.

 

the bitstream is ok,the download.bit is ok

 

i tried to work with bootloop.elf and the slide_show.elf the result is the same (nothing). 

 

the ace file is generated but it doesn't work, if you have any suggestions ? please tel me. 

 

 

 

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Participant camarada
Participant
9,052 Views
Registered: ‎06-05-2009

Re: ACE FILE PROBLEM

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Hi.

I have the same problems. My generated ACE file doesn't work. I tried to create ace file with genace tcl script file. What could be wrong in ace file creation?

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Xilinx Employee
Xilinx Employee
9,043 Views
Registered: ‎08-07-2007

Re: ACE FILE PROBLEM

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Please clarify what you mean by not work.

 

What's the status of the LED for SystmACE? Was the configuration of FPGA successful (DONE goes high)? Can you manually connect to the processor with XMD if the configuration succeed?

 

-XF

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Participant camarada
Participant
9,016 Views
Registered: ‎06-05-2009

Re: ACE FILE PROBLEM

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Thanks for the answer. Configuration is successful, software program works propely. I create ACE file with genace.tcl and save ACE file on the CF card. I left old (default) bootloader which ask for a configuration number. When program reset in the configuration that corresponds to my ACE file, red led lights up. I'm not sure, but I think it is the System ACE led. Help please.
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Xilinx Employee
Xilinx Employee
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Registered: ‎08-07-2007

Re: ACE FILE PROBLEM

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If you put hte ACE file into the root directory of the CF card, please remove the .ini file from the CF card and try again.

 

-XF

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Participant camarada
Participant
8,973 Views
Registered: ‎06-05-2009

Re: ACE FILE PROBLEM

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No my ACE file is in cfg(x) directory. xilinx.sys file is in root. All configs have been set properly. I don't understand what .ini file you meen. 

I think problem is in my ACE file. When I'm create it with genace without -start_address option, i get the message "elf file doesn't contain start address" however this one is specified in the elf file as 0x00. I have specified it with -start_address option, and then ace file creation is successful. 

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-07-2007

Re: ACE FILE PROBLEM

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I meant .sys file. Haven't been using it for a while, so got the wrong name.

 

 

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Participant camarada
Participant
8,289 Views
Registered: ‎06-05-2009

Re: ACE FILE PROBLEM

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But I'm interesting about an existing of many configurations as now.

I think about ace file creation problem. Can you tell me why when I use genace.tcl with elf file, I get message "elf file doesn't contain start address."?

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Participant camarada
Participant
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Registered: ‎06-05-2009

Re: ACE FILE PROBLEM

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My problem was solved. It was problem of my code. Thanks.
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Participant camarada
Participant
7,968 Views
Registered: ‎06-05-2009

Re: ACE FILE PROBLEM

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Hello, all. My problem with ace file generation has a long history.

For first I created ace-file for ml505 board and mdm target in EDK 10.1 (updated to 10.2) using c:\Xilinx\10.1\EDK\data\xmd\genace.tcl. Ace file was generated but it wasn't working.

Then I found the genace tcl in WorkspaceDirectory/data. When I used ace-file generated with this genace.tcl it became to work

 

Now I'm using EDK 11.1(updated to 11.2). There is no any tcl-file in WorkspaceDirectory/data. I tried with c:\Xilinx\11.1\EDK\data\xmd\genace.tcl. Result was the same. But I found out that FPGA programmed properly (when I used SDK to load program after powering on of the board (System ACE bootload) all was ok). DONE led is on and even Sysace Stat led is on.

 

Help me please.

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-07-2007

Re: ACE FILE PROBLEM

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Could you post the command that you used to generate the ACE file?
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Participant camarada
Participant
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Registered: ‎06-05-2009

Re: ACE FILE PROBLEM

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Thanks for the answer. I'm using

xmd -tcl genace.tcl -target mdm -hw implementation/download.bit -board ml505 -elf PathToElf -ace system.ace -start_address 0x0

Message Edited by camarada on 10-14-2009 08:41 AM
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Xilinx Employee
Xilinx Employee
7,944 Views
Registered: ‎08-07-2007

Re: ACE FILE PROBLEM

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Hi Camarada,

 

The command line looks fine.

 

Please go ahead and open a Web Case with Xilinx Technical Support. Please upload the bitstream and elf files when opening the case.

 

-Felix

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Participant camarada
Participant
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Registered: ‎06-05-2009

Re: ACE FILE PROBLEM

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Hello, Felix. WebCase demands one day for registration but I have not much time. I'll upload these files to the forum. Thank you for the help.
Message Edited by camarada on 10-14-2009 01:22 PM
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Xilinx Employee
Xilinx Employee
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Registered: ‎08-07-2007

Re: ACE FILE PROBLEM

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The ACE file works on my ml505 board.

 

I can see the LEDs being lit.

 

there's a memory test applicaiton intialized in your bitstream. When configured with ACE file, the test memory applicaiton won't be finished because it will be replaced by the new applicaiton in the ACE (leds.elf). This is the correct behavior. Is this the problem that you were referring to?

 

-Felix

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Participant camarada
Participant
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Registered: ‎06-05-2009

Re: ACE FILE PROBLEM

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Felix, Your ace works! The most important for me is version of EDK you used for a preparing of ace-file. My problem not in TestMemory app. Now, I know that my problem is in ace-file generation. I send you my ace-file, please try to load it. Can you upload your tcl script and your command line for ace-file creation? Thanks a lot.

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-07-2007

Re: ACE FILE PROBLEM

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I'm using EDK 11.3 and your command line.
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Registered: ‎10-12-2009

Re: ACE FILE PROBLEM

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Hi people,

I have some similar problem:

we are working on ml 506 platform and have problem with Ethernet.When we configure FPGA from SDK with *.bit and *.elf every thing is ok. Ethernet link is established and I can ping platform. Application is simple TCP server based on LwIP with UART used for debugging. 

Then we create SystemACE file according to the user guide http://www.xilinx.com/products/boards/ml505/docs/ml505_bsb_std_ip_addition.pdf and copy it to CF.

 

We used CF card to boot ml506,  everything works fine, UART debug messages seems fine, LED diode which indicated link speed is on (we tried all speed 10/100/1000), but when I ping platform there is no response (diode which indicated that packet is received RX blinks but TX never). Based on debug messages It seems that LwIP doesn't recevie packets at all. If we reload the software from SDK (with hardware configured from CF), application starts working!

 

Also, I've tried Web server demo application provided with the board from CF and it works fine.

 

Any ideas what may cause this problem? 

 

 

 

Message Edited by dragan.topalovic on 10-14-2009 01:54 PM
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Participant camarada
Participant
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Registered: ‎06-05-2009

Re: ACE FILE PROBLEM

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Phelix, Have you tried to load my ace file?
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Highlighted
11,197 Views
Registered: ‎10-12-2009

Re: ACE FILE PROBLEM

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Previously I used Xilinx EDK 11.2.

When update to the 11.3 problem was solved. 

genace.tcl from 11.2 have some bags.

 

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Xilinx Employee
Xilinx Employee
8,866 Views
Registered: ‎08-07-2007

Re: ACE FILE PROBLEM

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Camarada,

 

I believe that you hit the issue mentioned in this AR

http://www.xilinx.com/support/answers/32700.htm

 

Please upgrade to 11.3.

 

-Felix

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Participant camarada
Participant
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Registered: ‎06-05-2009

Re: ACE FILE PROBLEM

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Felix and Dragan thanks a lot. Problem was solved with 11.3 genace.tcl script.
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Participant camarada
Participant
8,845 Views
Registered: ‎06-05-2009

Re: ACE FILE PROBLEM

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Hello, dragan, I have the same proble as you. Ping to FPGA have no response. Have you find solution?
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8,842 Views
Registered: ‎10-12-2009

Re: ACE FILE PROBLEM

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Yes I have, like I mention in upper discussion. Problem was in genace.tcl script. When I upgrade script to the version 11.3 problem was solved. You should look at jumpers J22, J23 to choose between sgmii or gmii maybe that is problem.
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Participant camarada
Participant
8,835 Views
Registered: ‎06-05-2009

Re: ACE FILE PROBLEM

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Thx, Dragan. When I used 11.3 tcl script with 11.2 EDK apps without net was working. Now I create ace file on 11.3 EDK and net's working now.

Thank you.

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