I'm trying to implement a project in EDK 11.4 with the following features:
i follow xapp 1041 and avnet's (Xilinx Spartan-3A 1800 DSP Starter Board MicroBlaze ll_temac and lwIP Optimized for TCP/IP Performance) tutorial..
i'm facing timing failure...
i recently read the answer:
i would like to ask if the timing failure is due to the PLL syste_synchronous compensation...?
Any ideas about how i can face this timing failure?