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Adventurer
Adventurer
8,951 Views
Registered: ‎10-28-2011

AXI slave connection of PCIe AXI bridge IP

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Hi:  

I'm creating a system with IPI which have Microblaze, DDR3 and PCIe interface.

When connecting the AXI PCIe bridge block, I got some problem.

Currently, I can access DDR3 through PCIe.

The path is Host PC ==> PCIe ==> AXI PCIe bridge ==> AXI interconnect ==> DDR3.

Now, I want to send data from Microblaze to Host PC as well, but don't know how to do it.

Tthe path I think should be : MicroBlaze ==> AXI interconnect ==> AXI PCIe bridge ==> PCIe ==> Host PC.

How should I connect the S_AXI_CTL and S_AXI port on AXI PCIe bridge?

Should S_AXI_CTL be connected? Is it also connected to M_AXI port of AXI interconnect?

Thanks a lot! 

 

David

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Xilinx Employee
Xilinx Employee
16,506 Views
Registered: ‎02-01-2008

Re: AXI slave connection of PCIe AXI bridge IP

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Connect both s_axi_ctl and s_axi to the interconnect. You probably will not use s_axi_ctl but it can be handy for dumping the configuration space and in case you want to dynamically change the AXI to PCIe BARs. The actual dataflow from microblaze to PCIe will be via the s_axi port. When you setup your address map, make sure the address range you've assigned to the s_axi port is also configured in the axi to pcie core.

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Xilinx Employee
Xilinx Employee
16,507 Views
Registered: ‎02-01-2008

Re: AXI slave connection of PCIe AXI bridge IP

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Connect both s_axi_ctl and s_axi to the interconnect. You probably will not use s_axi_ctl but it can be handy for dumping the configuration space and in case you want to dynamically change the AXI to PCIe BARs. The actual dataflow from microblaze to PCIe will be via the s_axi port. When you setup your address map, make sure the address range you've assigned to the s_axi port is also configured in the axi to pcie core.

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Adventurer
Adventurer
8,897 Views
Registered: ‎10-28-2011

Re: AXI slave connection of PCIe AXI bridge IP

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Hi Johnmcd:

 

@ johnmcd

Thanks for your info.

I connect s_axi_ctl and s_axi to the AXI interconnect in my system.

However, I still can't observe the data change on host PC, when Microblaze issues memory write to address 0X00000000.

Attached is the address map of my system and the settings in AXI-PCIE core.

I set the size to 1MB, and the address is automatically set to 0X00000000.

I want it to be mapped to PCIe ( system memory on host) 0XFF000000.

Can you kindly help check if there's anything wrong with my settings?

Thanks a lot! 

 

David

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Xilinx Employee
Xilinx Employee
8,889 Views
Registered: ‎02-01-2008

Re: AXI slave connection of PCIe AXI bridge IP

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This setup looks a bit dangerous because you are mapping PCIe->AXI to address 0x00000000 which will inturn get decoded and go back out to PCIe land.

 

The M_AXI port from pcie probably only needs access to mig and maybe uart. The microblaze Data port address space looks correct. Any access from microblaze to address 0x00000000 will get decoded by the interconnect and passed to the S_AXI port on the pcie bridge. Then, the pcie bridge translates the axi address 0x00000000 to the PCIe address 0xFF000000.

 

I'm not a PCIe guru but I believe the software on the host will need to configure its pcie bridge in order to allow access to motherboard resources from the development board. On a linux host, the pcie driver would be responsible to map host memory or motherboard resources to be accessable from the development board.

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Adventurer
Adventurer
8,829 Views
Registered: ‎10-28-2011

Re: AXI slave connection of PCIe AXI bridge IP

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Hi Johnmcd:

 

Thanks a lot for your response! :)

 

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