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tkar
Observer
Observer
478 Views
Registered: ‎09-28-2017

AXI-stream FIFO stops working

Hello,

I am using an Axi Stream FIFO to read streamed data from a custom PL. The data clock is very slow (several Hz) and the normal operation is correct. I poll the FIFO if data is available and output it via Ethernet using LwIP.

if (XLlFifo_iRxGetLen(&ResultFifo) > 0){
	FifoBytes = FifoReceive(&ResultFifo, DestinationBuffer);
	memcpy(TXdata, DestinationBuffer, FifoBytes);
	tcp_send_packet(mypcb, FifoBytes);
}
int FifoReceive (XLlFifo *InstancePtr, u32* DestinationAddr){
	static u32 ReceiveLength;
	int Status;
	int i;
	u32 RxWord;

	ReceiveLength = (XLlFifo_iRxGetLen(InstancePtr));
	//xil_printf("RecvLength: %d \n\r", ReceiveLength);
	if (ReceiveLength > NET_TCP_BUFFER){					// do not  read more bytes than available for send buffer (normally not possible because of FIFO hardware = 512 Bytes)
		ReceiveLength = NET_TCP_BUFFER;
	}
	for ( i=0; i < ReceiveLength; i++){
			//RxWord = 0;
			RxWord = XLlFifo_RxGetWord(InstancePtr);
			*(DestinationAddr+i) = RxWord;
		}
	Status = XLlFifo_iRxOccupancy(InstancePtr);
	return ReceiveLength;
}

However when I stop the PL and start it again, in some cases I get a confusing behavior with the FIFO being displayed as filled (XLlFifo_iRxGetLen(&ResultFifo) = 2056, Fifo depth is 512 with 32 bit width in Vivado). Then the Ethernet connection is lost, in the UART I get "unknown temac type" error.

For the purpose of debugging I read the Fifo Status right after stopping the PL. As I thought I would need a reset of the FIFO to solve this problem, I do a XLlFifio_Reset and read the status again. I hope you can help me to find my mistake by the status register values:

 ISR after stopping: 0xA4000000, after reset: 0x01900000

Status register before the new transmission fails:

ISR after stopping: 0xA5900000, after reset: 0x01980000

 

Best regards

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1 Reply
tkar
Observer
Observer
401 Views
Registered: ‎09-28-2017

Found a solution to my problem:

The AXI4-Stream Data Width Converter which is driving the input of the FIFO asserted a constant '1' on the tvalid signal when I stopped my custom PL. I now connected it through a Utility Vector Logic working as an AND and gated the tvalid with my PL reset/halt signal.

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