05-31-2016 09:52 AM
First of all sorry for my bad english, I hope you can still understand what I am asking.
Here is a short description of what I want to do:
A system that has a golden version of RTL + microblaze code in a flash memory, and another version of RTL + microblaze code in the same memory but at a specific offset.
I already have a custom driver that allow me to write to my flash memory and send a new firmware or microblaze code through ethernet.
Thus the only thing missing for my whole system to work is some sort of fallback mechanism where the system reverts to the golden code if something goes wrong when trying to boot from the newer code. I believe this is something that can be done with spartan 6 on xilinx ISE but I'm not sure how to do it. Any help is appreciated.
05-31-2016 12:48 PM
Ok so I found this link here: https://forums.xilinx.com/t5/Configuration/Spartan-6-Fallback-Multiboot-Configuration/m-p/438250#M225
I followed every step but I get stuck on the "merging two mcs" part. I tried to copy the content of my header.mcs into the dual_image.mcs but impact generates an error when I program the flash memory. What is the correct way to merge the two mcs?
05-31-2016 08:30 PM
What is the error that you are seeing?
06-01-2016 10:27 AM - edited 06-01-2016 10:31 AM
When I follow the instructions in the thread I linked, it seems like the header gets compiled for spix8 instead of spix1 (according to information given by impact). I don't know enough about these file formats to fix the problem myself by directly editing the code. Could my issues be caused by this?
06-01-2016 10:34 AM - edited 06-01-2016 10:36 AM
While we're at it, where can I find information on the instruction codes found in the header? I'm talking about the opcodes found in UG380, page 134. For example:
3261: Type 1 Write 1 Words to GENERAL_1
I haven't been able to find the list of the opcodes used to write to certain registers. Knowing the register address doesn't seem to help with this.