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bejarub
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Registered: ‎05-06-2013

All DDR Locate constraints are removed during Translate ...

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Hi,

 

I try to create a XPS system with a Microblaze and a DDR3 controller. Synthesis runs without any warnings, but in the translate process for all DDR3 related constraints the target object can't be found (assuming I interpret the warnings properly).

My workflow is as followed: Create ISE project in 14.5/14.6, create XMP/XPS project, add DDR controller in XPS, create top module, create ucf file, implement the design.

 

I have tried several setups and settings but none worked, so I appreciate every hint.

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htsvn
Xilinx Employee
Xilinx Employee
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Registered: ‎08-02-2007

Hi,

 

Let us take a step back here.

 

Can you simply configure the memory controller and just apply the other peripheral constraints?

 

Looking at the documentation page 37 of this document the constraints for memory controller are automatically included in _xps folder and they need not be included in the actual UCF.

http://www.xilinx.com/support/documentation/ip_documentation/mig/v3_92/ug406.pdf

 

Can you try this?

 

--HS

 

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siktap
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Registered: ‎06-14-2012

Did you copy your system.ucf to toplevel.ucf?

 

You would try to use */ in front of DDR constraints.

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bejarub
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Registered: ‎05-06-2013

In the system.ucf there is only a clock definition for 200MHz (see system.ucf).

I have added */ in front of every DDR constraint. The result were the same warnings as before (without the */ ), is this the correct behavior? Temporary project files have been deleted before the new implementation run (Cleanup project files).

 

 

 

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bejarub
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Registered: ‎05-06-2013

I have also added the CLK constraint from the system.ucf (created by XPS), but the output is same.

However I have added a random Location constraint, which results into the following error message:

 

  ERROR:ConstraintSystem:58 - Constraint

    <NET "*/ABCDEF0123456789" LOC="M17" |> [E:/DDR3/system_3_con.ucf(29)]:

    NET "*/ABCDEF0123456789" does not match any design objects.
  ERROR:ConstraintSystem:58 - Constraint

    <IOSTANDARD = "LVCMOS33" |>[E:/DDR3/system_3_con.ucf(29)]:

    NET "*/ABCDEF0123456789" does not match any design objects.
  ERROR:ConstraintSystem:58 - Constraint

    <SLEW = "SLOW";>[E:/DDR3/system_3_con.ucf(29)]:

    NET "*/ABCDEF0123456789" does not match any design objects.

 

This is confusing to me, since I'm not sure what's the difference between "...does not match any design objects..." and  "...target design for the Locate constraint could not be found..."?!

 

Apart from the error, the */ is now also present in the message.

 

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siktap
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Registered: ‎06-14-2012

Can you go ahead with the implementation and check if these constraints are being adhered to? 

 

I also see that 

G NgdBuild:1012 - The constraint <NET "axi_7series_ddrx_0_ddr_ba_pin<2>" LOC = AA17> is overridden on
the design object axi_7series_ddrx_0_ddr_ba_pin<2> by the constraint <NET
"*/axi_7series_ddrx_0_ddr_ba_pin<2>" LOC = "AA17" |> [E:/Hardware/DDR3_a2/kx1_mb0.ucf(90)].

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bejarub
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Registered: ‎05-06-2013

Without the random Locate constraint the implementation and bitstream generation complete with warnings but successful.

 

Do you have an idea what's the meaning of the "...target object for Locate constraint..."warnings, alternatively what's the difference between the "...target object for Locate constraint..."warning and the "...does not match any design objects."error?

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siktap
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Scholar
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Registered: ‎06-14-2012

The target object is issued when there is incompatbility between the object and the constraint defined.The target object type of meesage might come from duplicated constraints.

 

The doesnt match kind of warning is issued when there is a name mismatch or the tool is unable to find the exact design cell.

 

Now that the implementation goes succesfully, can you check if DDR loc constraints are being taken. You could open the nc file in FPGA Editor and check for any DDR port that you had a loc assigned.

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htsvn
Xilinx Employee
Xilinx Employee
7,189 Views
Registered: ‎08-02-2007

Hi,

 

Let us take a step back here.

 

Can you simply configure the memory controller and just apply the other peripheral constraints?

 

Looking at the documentation page 37 of this document the constraints for memory controller are automatically included in _xps folder and they need not be included in the actual UCF.

http://www.xilinx.com/support/documentation/ip_documentation/mig/v3_92/ug406.pdf

 

Can you try this?

 

--HS

 

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Give Kudos to a post which you think is helpful and reply oriented.
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bejarub
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Registered: ‎05-06-2013

Hi,

 

yes that caused the problem. I have tried to remove the DDR constraints and implement the design again and the warnings don't apperear again.

I made the mistake and assumed that the UCF-files created by the wizards were templates and have to be added to the top level UCF.

 

Thanks a lot!

 

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