Hi there. I have a weird problem. I have a fairly simple design written in VHDL and C - bare metal. It works without issue, but then without me changing anything, the system runs slow.
It simply reads a memory location 128 times. I time it with an oscilloscope and it takes 25 micro seconds when working. Suddenly, after redownloading the bit file to the demo board (ZC702), it now takes 40 micro seconds. I have cycled power to the demo board, rebooted the PC and restarted SDK. This happened once before and I fixed it by cycling the power to the board, but this time it doesn't work. Note that I made no changes to the VHDL or the C code.
So for the purpose of troubleshooting, I modified my C code to print out the value of some registers. Then, for an older project known to work, I manually copied the files from the hw subdirectory into the hw_platform_0 subdirectory, overwriting the files already there. I also did not allow SDK to recompile/build anything. I then used the older project to program the dev board and ran the C code via SDK. Everything worked at the proper speed.
Then I loaded the the original project that started this post and without changing anything, it also ran at the proper speed. Comparing the print out of the registers I was looking at, such as the clock registers (all of them), the only difference was the FPGA0_CLK_CTRL register.
In the slow system, the register was: 0x100A00 and in the correct faster system, the register was: 0x100500. This accounts for the system being slower since this register controls the AXI bus and other peripherals. The memory I am reading 128 times is actually a FIFO in the PL section.
So now I know what changed but not why it changed or how to make sure it doesn't change again. Does anybody have any ideas about this?