I am trying to create a Microblaze system using Asynchronous FSL cores. The Microblaze is running at 100MHz and the cores are running at 125MHz. I am also debugging with SDK/XMD and Chipscope Pro on one of the FSL cores.
BEGIN fsl_v20 PARAMETER INSTANCE = fslreg_access_0_to_microblaze_0_0 PARAMETER HW_VER = 2.11.a PARAMETER C_ASYNC_CLKS = 1 PARAMETER C_READ_CLOCK_PERIOD = 8000 PARAMETER C_IMPL_STYLE = 1 PARAMETER C_FSL_DEPTH = 512 PORT SYS_Rst = sys_bus_reset PORT FSL_M_Clk = fsl_clk_s PORT FSL_S_Clk = sys_clk_s END
BEGIN fslreg_access PARAMETER INSTANCE = fslreg_access_0 PARAMETER HW_VER = 1.00.a BUS_INTERFACE MFSL = fslreg_access_0_to_microblaze_0_0 BUS_INTERFACE SFSL = microblaze_0_to_fslreg_access_0_0 PORT FSL_Clk = sys_clk_s PORT REG_Write = REG_Write PORT REG_DataOut = REG_DataOut PORT REG_DataIn = REG_DataIn PORT REG_Address = REG_Address PORT DEBUG_Trigger = fslreg_access_0_DEBUG_Trigger_to_chipscope_ila_1 PORT DEBUG_Data = fslreg_access_0_DEBUG_Data PORT REG_Clk = fsl_clk_s END
BEGIN fsl_v20 PARAMETER INSTANCE = microblaze_0_to_fslreg_access_0_0 PARAMETER HW_VER = 2.11.a PARAMETER C_ASYNC_CLKS = 1 PARAMETER C_READ_CLOCK_PERIOD = 8000 PARAMETER C_IMPL_STYLE = 1 PARAMETER C_FSL_DEPTH = 512 PORT SYS_Rst = sys_bus_reset PORT FSL_S_Clk = fsl_clk_s PORT FSL_M_Clk = sys_clk_s END
The parameters of the MSFL and SFSL cores are shown above. I am not sure that this is the correct way to connect the clocks to the fsl_v20 cores or not. I believe that the sys clock (100MHz) is correctly connected to the Microblaze side of the bus, and the fsl clock (125MHz) is connected to the fslreg_access side, but this configuration is not working anywhere near as reliably as the synchronous version was.
Is there any examples of an Asynchronous FSL system? Google and Xilinx searches have failed me so far.