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Visitor tcat
Visitor
486 Views
Registered: ‎04-02-2017

Automatic BMM file creation from Verilog

Hi,

 

I am learning Verilog, but do not know enough to help myself, eventhough I have read BMM examples and Data2Mem guide. 

I need to recode the below code,

 

module PROM (input clk,
input [8:0] adr,
output reg [31:0] data);

reg [31:0] mem [511: 0];
initial $readmemh("../prom.mem", mem);
always @(posedge clk) data <= mem[adr];

endmodule

 

into this example to put out BMM after synthesis,

 

 

RAMB16 #(.INIT_fl("file.mem")
...)
ramb16_0 ( <port mapping>);

 

The idea is to do a quick change of `prom.mem' using Data2Mem tool, as the full synthesis takes 12 minutes on my platform. I may need few iterations of `prom.mem' as part of learning.

 

Perhaps when I learn more about BRAM and address ranges I could assemble BMM by hand myself, but not now.

 

Many thanks

Tomas

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