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Adventurer
Adventurer
372 Views
Registered: ‎11-27-2010

Baremetal APU a53 Xil_SetTlbAttributes

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Hi All,

        1. I am running BareMetal Application on ARM a-53 core. [zcu102 board]

         2. I reserved a NON Caching memory by using this function  Xil_SetTlbAttributes((INTPTR)0x40000000, NORM_NONCACHE);

        3. Function requires the starting address and inside the function it sets attribute for memory range of 2MB

if(Addr < ADDRESS_LIMIT_4GB){
/* block size is 2MB for addressed < 4GB*/
block_size = BLOCK_SIZE_2MB;
section = Addr / block_size;
ptr = &MMUTableL2 + section;
}

questions: - 

[1] so my question is where is this restriction of 2MB coming from, why not less than 2MB?

[2] I could not find much information on the arm a-53 manual. Please point me to it.

 

Thanks

 

 

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Moderator
Moderator
363 Views
Registered: ‎10-06-2016

Re: Baremetal APU a53 Xil_SetTlbAttributes

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Hi @optivareddy,

The translation table has been configured to use 4KB granularity with 2MB section size for the initial 4GB of memory as you can see in the translation_table for A53 within the standalone OS code. That's why the API for TLB modification makes use of the 2MB block size information.

You can find more info about it within the ARMv8 PG rather than the A53 TRM.

When you use a 4kB granule size, the hardware can use a 4-level look up process. The 48-bit address has nine address bits per level translated, that is 512 entries each, with the final 12 bits selecting a byte within the 4kB coming directly from the original address. 
Bits 47:39 of the Virtual Address index into the 512 entry L0 table. Each of these table entries spans a 512 GB range and points to an L1 table. Within that 512 entry L1 table, bits 38:30 are used as index to select an entry and each entry points to either a 1GB block or an L2 table. Bits 29:21 index into a 512 entry L2 table and each entry points to a 2MB block or next table level. At the last level, bits 20:12 index into a 512 entry L2 table and each entry points to a 4kB block.

Regards


Ibai
Don’t forget to reply, kudo, and accept as solution.
2 Replies
Moderator
Moderator
364 Views
Registered: ‎10-06-2016

Re: Baremetal APU a53 Xil_SetTlbAttributes

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Hi @optivareddy,

The translation table has been configured to use 4KB granularity with 2MB section size for the initial 4GB of memory as you can see in the translation_table for A53 within the standalone OS code. That's why the API for TLB modification makes use of the 2MB block size information.

You can find more info about it within the ARMv8 PG rather than the A53 TRM.

When you use a 4kB granule size, the hardware can use a 4-level look up process. The 48-bit address has nine address bits per level translated, that is 512 entries each, with the final 12 bits selecting a byte within the 4kB coming directly from the original address. 
Bits 47:39 of the Virtual Address index into the 512 entry L0 table. Each of these table entries spans a 512 GB range and points to an L1 table. Within that 512 entry L1 table, bits 38:30 are used as index to select an entry and each entry points to either a 1GB block or an L2 table. Bits 29:21 index into a 512 entry L2 table and each entry points to a 2MB block or next table level. At the last level, bits 20:12 index into a 512 entry L2 table and each entry points to a 4kB block.

Regards


Ibai
Don’t forget to reply, kudo, and accept as solution.
Xilinx Employee
Xilinx Employee
329 Views
Registered: ‎09-01-2014

Re: Baremetal APU a53 Xil_SetTlbAttributes

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According to "ARM Architecture Reference Manual ARMv8, for ARMv8-A architecture profile"

Block descriptor
Gives the base address and attributes of a block of memory, as follows:
4KB translation granule
• For a first-level Block descriptor, bits[47:30] are bits[47:30] of the output
address. This output address specifies a 1GB block of memory.
• For a second-level descriptor, bits[47:21] are bits[47:21] of the output
address.This output address specifies a 2MB block of memory.
16KB translation granule
For a second-level Block descriptor, bits[47:25] are bits[47:25] of the output
address.This output address specifies a 32MB block of memory.
64KB translation granule
For a second-level Block descriptor, bits[47:29] are bits[47:29] of the output
address.This output address specifies a 512MB block of memory.
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