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Registered: ‎03-24-2009

Base System Builder Error on ML505 Board

i used base system builder on ml505 board, when i select the Tri-Mode Ethernet MAC, at netlist generation xps gives an error message below,

 

********************************************************************************************* 

Writing module to "hard_ethernet_mac_wrapper_async_fifo_v6_1_2.ngo"...

Loading design module

"D:\ISE_Design\calisma\bsb_design_creation\mlm505_bsb_design_own\implementation\

hard_ethernet_mac_wrapper\hard_ethernet_mac_wrapper_async_fifo_v6_1_2.ngo"...

ERROR:NgdBuild:76 - File

"D:\ISE_Design\calisma\bsb_design_creation\mlm505_bsb_design_own\implementati

on\hard_ethernet_mac_wrapper\hard_ethernet_mac_wrapper_async_fifo_v6_1_2.ngo"

cannot be merged into block

"Hard_Ethernet_MAC/I_RX0/I_RX_TEMAC_IF/I_RX_CL_IF/I_RX_CLIENT_FIFO"

(TYPE="hard_ethernet_mac_wrapper_async_fifo_v6_1_2") because one or more pins

on the block, including pin "Dout<19>", were not found in the file. Please

make sure that all pins on the instantiated component match pins in the

lower-level design block (irrespective of case). If there are bussed pins on

this block, make sure that the upper-level and lower-level netlists use the

same bus-naming convention.

Executing edif2ngd -noa

"D:\ISE_Design\calisma\bsb_design_creation\mlm505_bsb_design_own\implementation\

hard_ethernet_mac_wrapper_async_fifo_v6_1_1.edn"

"hard_ethernet_mac_wrapper_async_fifo_v6_1_1.ngo"

Release 10.1.03 - edif2ngd K.39 (nt)

Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.

INFO:NgdBuild - Release 10.1.03 edif2ngd K.39 (nt)

INFO:NgdBuild - Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.

PMSPEC -- Overriding Xilinx file <D:/Xilinx/10.1/EDK/data/edif2ngd.pfd> with

local file <D:/Xilinx/10.1/ISE/data/edif2ngd.pfd>

Writing module to "hard_ethernet_mac_wrapper_async_fifo_v6_1_1.ngo"...

Loading design module

"D:\ISE_Design\calisma\bsb_design_creation\mlm505_bsb_design_own\implementation\

hard_ethernet_mac_wrapper\hard_ethernet_mac_wrapper_async_fifo_v6_1_1.ngo"...

ERROR:NgdBuild:76 - File

"D:\ISE_Design\calisma\bsb_design_creation\mlm505_bsb_design_own\implementati

on\hard_ethernet_mac_wrapper\hard_ethernet_mac_wrapper_async_fifo_v6_1_1.ngo"

cannot be merged into block

"Hard_Ethernet_MAC/I_TX0/I_TX_TEMAC_IF/I_TX_CL_IF/I_TX_CLIENT_FIFO"

(TYPE="hard_ethernet_mac_wrapper_async_fifo_v6_1_1") because one or more pins

on the block, including pin "Wr_count<3>", were not found in the file.

Please make sure that all pins on the instantiated component match pins in

the lower-level design block (irrespective of case). If there are bussed

pins on this block, make sure that the upper-level and lower-level netlists

use the same bus-naming convention.

***************************************************************************************************

 

i also download base system builder application

 

http://www.xilinx.com/products/boards/ml505/ml505_10.1_3_1/docs/ml505_bsb_design_creation.pdf

 

unfortunately i got the same error.

 

 

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