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Voyager
Voyager
7,322 Views
Registered: ‎02-10-2012

Basic Question regarding custome IP created using the CIP Wizard of the EDK

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Hello

 

I had 2 basic question regarding the use of the Bus2IP_Data , IP2Bus_Data and the Bus2IP_WrCE signals :

 

Question 1 ) Going by the exaple for slave register write and read process that is auto generated when one creates a custome IP the Bus2IP_Data signal is used mainly to communicate from the Microblaze C code to the slave registers implemented in VHDL right ? I mean supposed I want to write to a slave register from my Microblaze C code all I have to do is the following :

 

volatile Xuint32 *gptr = base address of the created ip + offset to the slave register ;

*(gptr)= 0x1;

 

So what is the use of the signal IP2Bus_Data ??? If i want to send a value to the MicroBlaze C code from my VHDL slave registers I can as well do :

 

volatile u32 incoming_data

incoming_data = *(base address of created ip + offset of the slave register I want to read from);

 

Is the IP2Bus_Data used for any other special purpose ?

 

Question 2 ) Is the Bus2IP_WrCE signal active only during an active write operation ? as in once the write to the slave register is over is this signal automatically deactivated ?

 

Would be greateful if any one could help me with this or point me to a document that contains information especially about these signals. The only place I could find inofrmation about these signals was in the box of the CIP wizard when the signal selection menu was reached. I felt that much is not sufficient to fully understand the information regarding these signals.

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Teacher
Teacher
9,345 Views
Registered: ‎11-14-2011

To answer succintly but with a more hardware angle - I can't really quote a document about the AXI bus but I have used the PLB quite a lot recently:

 

1. As you rightly state, the Bus2IP_Data bus is used to carry data TO the register. Note that data needn't originate from "C code" but if it does in your case, so be it. There is no problem.

 

The IP2Bus_Data does the reverse - it is used to carry data from the register to the bus (AXI in your case). From a software level of abstraction, you see no difference in HOW the data reaches the processor. However, in actual hardware, two DIFFERENT internal bus signals are used. This is just how the slave IP handles the bidirectionalism of the bus. Try to visualise how you would implement a bidirectional signal or bus in physical hardware (as this is what you are asking your synthesiser to do).

 

Therefore, if you were to use chipscope in your design, looking at both Bus2IP_Data and IP2Bus_Data, on a write transaction from the processor to your IP register, you would see the data on the Bus2IP_Data bus. On a read transaction from the same register, the data would appear on the IP2Bus_Data bus.

 

2. Yes. Once the target IP asserts the write acknowledge signal (this is up to your IP, i.e. you must ensure that you encode this assertion), the Bus2IP_WrCE strobe is automatically deasserted. Note also that your IP must also encode the acknowledge's deassertion, too.

 

Hope this helps.

 

Regards,

 

Howard

 

 

----------
"That which we must learn to do, we learn by doing." - Aristotle

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Scholar
Scholar
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Registered: ‎04-07-2008

Maybe this document will help:

 

C:\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_slave_single_v1_01_a\doc\plbv46_slave_single.pdf

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Voyager
Voyager
7,313 Views
Registered: ‎02-10-2012

Hello Golson

 

Thank you for your quick response. The document you have provided is for a PLB system. Does the signals have the same functionality in the AXI4 Lite system ? I am sorry i forgot to mention about the AXI Lite system earlier. My custome IP is based on an AXI4 Lite system ..

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Voyager
Voyager
7,311 Views
Registered: ‎02-10-2012

Okay I searched for a similar document with the AXI4 Lite and found it! Great this has some more Information.

http://www.xilinx.com/support/documentation/ip_documentation/axi_lite_ipif_ds765.pdf

 

However all the information mentioned about the IP2Bus_Data is that :

Input Read Data bus from the user IP. Data is qualified with the assertion of IP2Bus_RdAck signal and the rising edge of the Bus2IP_Clk.

 

This is also the exact information that comes in the CIP Wizard window. I am still left with the confusion about my 1st Question.

 

 

..

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Scholar
Scholar
7,301 Views
Registered: ‎04-07-2008

Restate your question. 

 

Looking at your C code it looks like it should be correct.  It is easier to use the macros supplied sometimes

which takes the C code complications away.

 

 

XIo_Out32(0x50000008, 0x00000001);  This would be to write to register Slave 2  offset 8 the value 1

 

 

and

 

 

do

{

   tempdata32 = XIo_In32(0x50000004);

   //xil_printf("empty = %08x \n\r", empty);

} while ( tempdata32 & 0x1 ); // looking for 512 bytes in FIFO

 

the above loop is reading slave reg 1 offset 4  bit 0 is checked to see when it goes to a zero

so it can drop through.

 

 

You can also look at the definition of the macros to see how they code the C code as a comparison to yours.

 

 

 

 

 

 

 

 

 

 

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Teacher
Teacher
9,346 Views
Registered: ‎11-14-2011

To answer succintly but with a more hardware angle - I can't really quote a document about the AXI bus but I have used the PLB quite a lot recently:

 

1. As you rightly state, the Bus2IP_Data bus is used to carry data TO the register. Note that data needn't originate from "C code" but if it does in your case, so be it. There is no problem.

 

The IP2Bus_Data does the reverse - it is used to carry data from the register to the bus (AXI in your case). From a software level of abstraction, you see no difference in HOW the data reaches the processor. However, in actual hardware, two DIFFERENT internal bus signals are used. This is just how the slave IP handles the bidirectionalism of the bus. Try to visualise how you would implement a bidirectional signal or bus in physical hardware (as this is what you are asking your synthesiser to do).

 

Therefore, if you were to use chipscope in your design, looking at both Bus2IP_Data and IP2Bus_Data, on a write transaction from the processor to your IP register, you would see the data on the Bus2IP_Data bus. On a read transaction from the same register, the data would appear on the IP2Bus_Data bus.

 

2. Yes. Once the target IP asserts the write acknowledge signal (this is up to your IP, i.e. you must ensure that you encode this assertion), the Bus2IP_WrCE strobe is automatically deasserted. Note also that your IP must also encode the acknowledge's deassertion, too.

 

Hope this helps.

 

Regards,

 

Howard

 

 

----------
"That which we must learn to do, we learn by doing." - Aristotle

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Voyager
Voyager
7,261 Views
Registered: ‎02-10-2012

Thank you Goldson and Howard!

Yes Howard , the information you provided is exactly what i was looking for! I went through the auto generated VHDL code again and I now see your point about the bidirectionalism of the bus! Perfect!

Coming to the Bus2IP_WrCE , if i understood you correctly the assertion and deassertion of the Bus2IP_WrCE is done AUTOMATICALLY rand the part I have to take care is to use the status of assertion and deassertion in the code correctly right ?

 

For example the write procedure is something like :

I assign the following

slv_reg_write_sel <= Bus2IP_WrCE(2 downto 0);

 

and then inside a process I do the following  :

case slv_reg_write_sel is
   when "100" =>
      for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
          if ( Bus2IP_BE(byte_index) = '1' ) then
              slv_reg0(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
          end if;
      end loop;
   when others => null;

end case;

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Teacher
Teacher
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Registered: ‎11-14-2011

Yes, this works fine (on inspection, anyway).

 

Bear in mind what I wrote about the Write Acknowledge. Your IP positively MUST assert and deassert this signal correctly for the transactions to complete correctly on the bus.

 

For registers, it is common to tie the acknowledge to the Chip Enable, so that the acknowledge is immediate. There is no latency for a direct register write anyway and this helps release the bus as fast as possible. So, in your case:

 

slv_wr_ack <= Bus2IP_WrCE(2) or Bus2IP_WrCE(1) or Bus2IP_WrCE(0);

 

Note this method will assert (and then deassert) the acknowledge regardless of the state of Bus2IP_BE. This can have the effect of gracefully terminating ANY transaction even if there is no real data to pass to a register - consider an incorrect byte lane targeting a register that is less than the data bus width. Careful that this is actually what you want.

 

Regards,

 

Howard

 

----------
"That which we must learn to do, we learn by doing." - Aristotle
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Voyager
Voyager
7,234 Views
Registered: ‎02-10-2012

Thank you Howard. My concept is clear now on this matter :) Thanks for taking time out to explain this.

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