04-07-2009 01:26 AM
I'm working with Xilinx Platform Studio and I'm trying to learn about Microblaze & Chipscope.
First, I redo exactly what is described in the Spartan3ADSP_MB_Example_10_1.pdf document and I inserted a chipscope_plbv46_iba and a chipscope_icon cores in my project. By doing this, I had no error when I generate Bitstream.
After that, I made my own project (which is quiet similar) with a chipscope_plbv46_iba and a chipscope_icon cores in my project. And when I generate Bitstream I got the following error for both of the cores:
Gathering HDL files for chipscope_icon_0 root...
Creating XST project for chipscope_icon_0...
Creating XST script file for chipscope_icon_0...
Creating XST instantiation file for chipscope_icon_0...
Running XST for chipscope_icon_0...
Not generating a VHDL simulation model
Not generating a Verilog simulation model
Skipping VHDL instantiation template for chipscope_icon_0...
Skipping Verilog instantiation template for chipscope_icon_0...
Successfully generated chipscope_icon_0.
ERROR:MDT - chipscope_icon_0 (chipscope_icon) - ERROR: Coregen did not generate
(procedure "::hw_chipscope_icon_v1_02_a::icon_generate" line 85)
invoked from within
Did somebody get the same error case?
I don't understand what is different in my own project and the Spartan3ADSP_MB_Example_10_1 project, where is the problem with these cores?
I really appreciate if someone can give me some help!
04-24-2011 05:16 AM
Hi , i dnt know answer to your question , but can you help me in finding some examples to begin with in microblaze , some basic ones !
03-18-2012 03:25 PM
I am getting the same error , please share how were u able to solve this problem
Thanks in advance
03-22-2012 06:47 AM
Nothing is visible when we click on the link which comes on this statement .
Also this is a problem with elaboration of the netlist platgen is not able to generate the core , which is specified in chipscope.xco file.
Since there is no comment or feedback or message from the tool we are unable to have a clue wats wrong , all other IPs including MDMs are getting successfully synthesized but chipscope one.