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Adventurer
Adventurer
4,020 Views
Registered: ‎12-01-2010

Clock generator problem?

Hello,

 

   I got an error when I generate the bitstream of my design during the MAP step.

 

ERROR:LIT:447 - CLKINSEL of PLL_ADV symbol    "physical_group_system_i/clock_generator_0/clock_generator_0/SIG_PLL0_CLKOUT0/system_i/clock_generator_0/clock_generator_0/PLL0_INST/Using_PLL_ADV.PLL_ADV_inst" (output    signal=system_i/clock_generator_0/clock_generator_0/SIG_PLL0_CLKOUT0) is a    constant 1 (choosing CLKIN1) but CLKIN1 is not an active signal.

 

Xilinx offical solution of #447 simply says:

 

"This issue has been fixed in the "clock_generator_v3_00_a" core and is available in EDK 11.1

at:  http://www.xilinx.com/xlnx/xil_sw_updates_home.jsp "

 

However, I am using XPS13.4 which has clock_generator_4_03_a. It's a newer version. But the problem still exist.

I cannot figure out where the problem is. Can anyone give me a hint to solve it?

 

Thanks,

 

Eric

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4 Replies
Adventurer
Adventurer
4,001 Views
Registered: ‎12-01-2010

any help, please??

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Teacher
Teacher
3,999 Views
Registered: ‎11-14-2011

Could you post your MHS file or a description of how your clock generator is configured/connected?

 

Regards,

 

Howard

 

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"That which we must learn to do, we learn by doing." - Aristotle
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Adventurer
Adventurer
3,985 Views
Registered: ‎12-01-2010

Thanks, Howard,

 

  This is my MHS file, hope you can help me to figure the problem out.

 

PARAMETER VERSION = 2.1.0

 

 

 PORT fpga_0_clk_1_sys_clk_pin = CLK_S, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000

 PORT fpga_0_rst_1_sys_rst_pin = sys_rst_s, DIR = I, SIGIS = RST, RST_POLARITY = 0

 

 

BEGIN microblaze

 PARAMETER INSTANCE = microblaze_0

 PARAMETER C_USE_BARREL = 1

 PARAMETER C_DEBUG_ENABLED = 1

 PARAMETER HW_VER = 8.20.b

 BUS_INTERFACE DLMB = dlmb

 BUS_INTERFACE ILMB = ilmb

 BUS_INTERFACE DPLB = mb_plb

 BUS_INTERFACE IPLB = mb_plb

 BUS_INTERFACE DEBUG = microblaze_0_mdm_bus

 PORT MB_RESET = mb_reset

END

 

BEGIN plb_v46

 PARAMETER INSTANCE = mb_plb

 PARAMETER HW_VER = 1.05.a

 PORT PLB_Clk = clk_125_0000MHz

 PORT SYS_Rst = sys_bus_reset

END

 

BEGIN lmb_v10

 PARAMETER INSTANCE = ilmb

 PARAMETER HW_VER = 2.00.b

 PORT LMB_Clk = clk_125_0000MHz

 PORT SYS_Rst = sys_bus_reset

END

 

BEGIN lmb_v10

 PARAMETER INSTANCE = dlmb

 PARAMETER HW_VER = 2.00.b

 PORT LMB_Clk = clk_125_0000MHz

 PORT SYS_Rst = sys_bus_reset

END

 

BEGIN lmb_bram_if_cntlr

 PARAMETER INSTANCE = dlmb_cntlr

 PARAMETER HW_VER = 3.00.b

 PARAMETER C_BASEADDR = 0x00000000

 PARAMETER C_HIGHADDR = 0x00001fff

 BUS_INTERFACE SLMB = dlmb

 BUS_INTERFACE BRAM_PORT = dlmb_port

END

 

BEGIN lmb_bram_if_cntlr

 PARAMETER INSTANCE = ilmb_cntlr

 PARAMETER HW_VER = 3.00.b

 PARAMETER C_BASEADDR = 0x00000000

 PARAMETER C_HIGHADDR = 0x00001fff

 BUS_INTERFACE SLMB = ilmb

 BUS_INTERFACE BRAM_PORT = ilmb_port

END

 

BEGIN bram_block

 PARAMETER INSTANCE = lmb_bram

 PARAMETER HW_VER = 1.00.a

 BUS_INTERFACE PORTA = ilmb_port

 BUS_INTERFACE PORTB = dlmb_port

END

 

BEGIN clock_generator

 PARAMETER INSTANCE = clock_generator_0

 PARAMETER C_CLKIN_FREQ = 100000000

 PARAMETER C_CLKOUT0_FREQ = 125000000

 PARAMETER C_CLKOUT0_PHASE = 0

 PARAMETER C_CLKOUT0_GROUP = NONE

 PARAMETER C_CLKOUT0_BUF = TRUE

 PARAMETER C_EXT_RESET_HIGH = 0

 PARAMETER HW_VER = 4.03.a

 PORT CLKIN = CLK_S

 PORT CLKOUT0 = clk_125_0000MHz

 PORT RST = sys_rst_s

 PORT LOCKED = Dcm_all_locked

END

 

BEGIN mdm

 PARAMETER INSTANCE = mdm_0

 PARAMETER C_MB_DBG_PORTS = 1

 PARAMETER C_USE_UART = 1

 PARAMETER HW_VER = 2.00.b

 PARAMETER C_BASEADDR = 0x84400000

 PARAMETER C_HIGHADDR = 0x8440ffff

 BUS_INTERFACE SPLB = mb_plb

 BUS_INTERFACE MBDEBUG_0 = microblaze_0_mdm_bus

 PORT Debug_SYS_Rst = Debug_SYS_Rst

END

 

BEGIN proc_sys_reset

 PARAMETER INSTANCE = proc_sys_reset_0

 PARAMETER C_EXT_RESET_HIGH = 0

 PARAMETER HW_VER = 3.00.a

 PORT Slowest_sync_clk = clk_125_0000MHz

 PORT Ext_Reset_In = sys_rst_s

 PORT MB_Debug_Sys_Rst = Debug_SYS_Rst

 PORT Dcm_locked = Dcm_all_locked

 PORT MB_Reset = mb_reset

 PORT Bus_Struct_Reset = sys_bus_reset

 PORT Peripheral_Reset = sys_periph_reset

END

 

BEGIN bridge_connect

 PARAMETER INSTANCE = bridge_connect_0

 PARAMETER HW_VER = 1.00.a

 PARAMETER C_BASEADDR = 0xce200000

 PARAMETER C_HIGHADDR = 0xce20ffff

 BUS_INTERFACE SPLB = mb_plb

END

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Teacher
Teacher
3,982 Views
Registered: ‎11-14-2011

I can't see anything obvious from your MHS.

 

What does the synthesis report state for the clock_generator module and for the top level design? Particularly regarding the clock input.

 

Regards,

 

Howard

 

P.S. This issue seems very similar to the message here

 

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"That which we must learn to do, we learn by doing." - Aristotle
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