06-08-2009 10:11 AM
I have an application that can be partitioned into two major parts. I was thinking to exploit the fact that my Virtex4 has 2 on-chip PowerPCs by mapping the two application parts onto the two PowerPCs. My question is the following: Is there any way to insert some kind of synchronization barriers in the C code so I can control the execution flow between the 2 PowerPCs? For example I would like to be able to send an acknowledgement from the 1st PowerPC to the 2nd one when the code execution on the 1st PowerPC arrives at a specific point, as shown below:
C code that runs on PowerPC1:
I hope my question is clear. :-) Any suggestions are most welcome!
06-08-2009 11:01 PM
I haven't used them myself, but you might want to look into the "XPS Mutex" and "XPS Mailbox" IPs.
06-08-2009 11:40 PM - edited 06-08-2009 11:42 PM
If memory serves me correctly, these cores first were deployed in the ML410 reference designs (http://www.xilinx.com/ml410-p) before eventually becoming integrated into EDK (maybe in 10.1). It may be useful to at least review the dual processor designs there.
Other useful resources:
http://www.xilinx.com/support/documentation/white_papers/wp262.pdf (Designing Multiprocessor Systems in Platform Studio)
http://www.xilinx.com/support/documentation/application_notes/xapp996.pdf (Dual Processor Reference Design Suite)
06-10-2009 10:22 AM
Hello JimmyB and Timpe,
I would like to thank you both very much for your feedback. It really gave me a nice start to work on my design! :-)