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Explorer
Explorer
7,826 Views
Registered: ‎12-05-2012

Connecting peripherals in XPS (EDK 14.2)

Hello guys,

 

I have tried to connect peripherals using xps first I tried to connect uart using the xps system assembly view by just selecting uart1 present in the I/O  and then implemented the sdk and it works perfectly .

Now I tried same with the I2C and tried to implement the peripheral tests in the sdk but it has an error

Can you suggest what could have gone wrong??

 

Thanks for your patience

 

 

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11 Replies
Xilinx Employee
Xilinx Employee
7,823 Views
Registered: ‎08-02-2011

Re: Connecting peripherals in XPS (EDK 14.2)

What's the error message?

 

Can you post your .mhs? Do you get any warnings from XPS?

www.xilinx.com
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Adventurer
Adventurer
7,815 Views
Registered: ‎04-11-2012

Re: Connecting peripherals in XPS (EDK 14.2)

Did you remember to upload the updated FPGA configuration first?  Also, remember that I2C requires interrupts, so make sure that you have an INTC and have connected the I2C interrupt up to it.

 

I had a problem where the INTC test would fail because it was already initialised from a previous run (and the relaunch apparently did not reset the CPU, although a reprogram does).  As a consequence of this later tests would also fail or hang.  Running "rst" in the XMD console window sorted that one out.

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Explorer
Explorer
7,810 Views
Registered: ‎12-05-2012

Re: Connecting peripherals in XPS (EDK 14.2)

The interrupts are disabled if you select I2c0 as it is MIO pin. It only has scl and sda lines 

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Explorer
Explorer
7,807 Views
Registered: ‎12-05-2012

Re: Connecting peripherals in XPS (EDK 14.2)

this is the warning message I have
WARNING:EDK:4181 - PORT: FCLK_CLK0, CONNECTOR: processing_system7_0_FCLK_CLK0 - floating connection - D:\Gujjeti_TEMP\thesis.srcs\sources_1\edk\EDK_design\EDK_design.mhs line 116
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Explorer
Explorer
7,806 Views
Registered: ‎12-05-2012

Re: Connecting peripherals in XPS (EDK 14.2)

HERE IS THE MHS file


# ##############################################################################
# Created by Base System Builder Wizard for Xilinx EDK 14.2 Build EDK_P.28xd
# Wed Dec 05 12:34:52 2012
# Target Board:  xilinx.com zc702 Rev C
# Family:    zynq
# Device:    xc7z020
# Package:   clg484
# Speed Grade:  -1
# ##############################################################################
 PARAMETER VERSION = 2.1.0


 PORT processing_system7_0_MIO = processing_system7_0_MIO, DIR = IO, VEC = [53:0]
 PORT processing_system7_0_PS_SRSTB = processing_system7_0_PS_SRSTB, DIR = I
 PORT processing_system7_0_PS_CLK = processing_system7_0_PS_CLK, DIR = I, SIGIS = CLK
 PORT processing_system7_0_PS_PORB = processing_system7_0_PS_PORB, DIR = I
 PORT processing_system7_0_DDR_Clk = processing_system7_0_DDR_Clk, DIR = IO, SIGIS = CLK
 PORT processing_system7_0_DDR_Clk_n = processing_system7_0_DDR_Clk_n, DIR = IO, SIGIS = CLK
 PORT processing_system7_0_DDR_CKE = processing_system7_0_DDR_CKE, DIR = IO
 PORT processing_system7_0_DDR_CS_n = processing_system7_0_DDR_CS_n, DIR = IO
 PORT processing_system7_0_DDR_RAS_n = processing_system7_0_DDR_RAS_n, DIR = IO
 PORT processing_system7_0_DDR_CAS_n = processing_system7_0_DDR_CAS_n, DIR = IO
 PORT processing_system7_0_DDR_WEB_pin = processing_system7_0_DDR_WEB, DIR = O
 PORT processing_system7_0_DDR_BankAddr = processing_system7_0_DDR_BankAddr, DIR = IO, VEC = [2:0]
 PORT processing_system7_0_DDR_Addr = processing_system7_0_DDR_Addr, DIR = IO, VEC = [14:0]
 PORT processing_system7_0_DDR_ODT = processing_system7_0_DDR_ODT, DIR = IO
 PORT processing_system7_0_DDR_DRSTB = processing_system7_0_DDR_DRSTB, DIR = IO, SIGIS = RST
 PORT processing_system7_0_DDR_DQ = processing_system7_0_DDR_DQ, DIR = IO, VEC = [31:0]
 PORT processing_system7_0_DDR_DM = processing_system7_0_DDR_DM, DIR = IO, VEC = [3:0]
 PORT processing_system7_0_DDR_DQS = processing_system7_0_DDR_DQS, DIR = IO, VEC = [3:0]
 PORT processing_system7_0_DDR_DQS_n = processing_system7_0_DDR_DQS_n, DIR = IO, VEC = [3:0]
 PORT processing_system7_0_DDR_VRN = processing_system7_0_DDR_VRN, DIR = IO
 PORT processing_system7_0_DDR_VRP = processing_system7_0_DDR_VRP, DIR = IO


BEGIN processing_system7
 PARAMETER INSTANCE = processing_system7_0
 PARAMETER HW_VER = 4.01.a
 PARAMETER C_DDR_RAM_HIGHADDR = 0x3FFFFFFF
 PARAMETER C_USE_M_AXI_GP0 = 0
 PARAMETER C_EN_EMIO_CAN0 = 0
 PARAMETER C_EN_EMIO_CAN1 = 0
 PARAMETER C_EN_EMIO_ENET0 = 0
 PARAMETER C_EN_EMIO_ENET1 = 0
 PARAMETER C_EN_EMIO_I2C0 = 0
 PARAMETER C_EN_EMIO_I2C1 = 0
 PARAMETER C_EN_EMIO_PJTAG = 0
 PARAMETER C_EN_EMIO_SDIO0 = 0
 PARAMETER C_EN_EMIO_CD_SDIO0 = 0
 PARAMETER C_EN_EMIO_WP_SDIO0 = 0
 PARAMETER C_EN_EMIO_SDIO1 = 0
 PARAMETER C_EN_EMIO_CD_SDIO1 = 0
 PARAMETER C_EN_EMIO_WP_SDIO1 = 0
 PARAMETER C_EN_EMIO_SPI0 = 0
 PARAMETER C_EN_EMIO_SPI1 = 0
 PARAMETER C_EN_EMIO_SRAM_INT = 0
 PARAMETER C_EN_EMIO_TRACE = 0
 PARAMETER C_EN_EMIO_TTC0 = 0
 PARAMETER C_EN_EMIO_TTC1 = 0
 PARAMETER C_EN_EMIO_UART0 = 0
 PARAMETER C_EN_EMIO_UART1 = 0
 PARAMETER C_EN_EMIO_MODEM_UART0 = 0
 PARAMETER C_EN_EMIO_MODEM_UART1 = 0
 PARAMETER C_EN_EMIO_WDT = 0
 PARAMETER C_EN_QSPI = 0
 PARAMETER C_EN_SMC = 0
 PARAMETER C_EN_CAN0 = 0
 PARAMETER C_EN_CAN1 = 0
 PARAMETER C_EN_ENET0 = 0
 PARAMETER C_EN_ENET1 = 0
 PARAMETER C_EN_I2C0 = 1
 PARAMETER C_EN_I2C1 = 0
 PARAMETER C_EN_PJTAG = 0
 PARAMETER C_EN_SDIO0 = 0
 PARAMETER C_EN_SDIO1 = 0
 PARAMETER C_EN_SPI0 = 0
 PARAMETER C_EN_SPI1 = 0
 PARAMETER C_EN_TRACE = 0
 PARAMETER C_EN_TTC0 = 0
 PARAMETER C_EN_TTC1 = 0
 PARAMETER C_EN_UART0 = 0
 PARAMETER C_EN_UART1 = 0
 PARAMETER C_EN_MODEM_UART0 = 0
 PARAMETER C_EN_MODEM_UART1 = 0
 PARAMETER C_EN_USB0 = 0
 PARAMETER C_EN_USB1 = 0
 PARAMETER C_EN_WDT = 0
 PARAMETER C_EN_DDR = 1
 PARAMETER C_EN_GPIO = 0
 PARAMETER C_FCLK_CLK0_FREQ = 50000000
 PARAMETER C_FCLK_CLK1_FREQ = 50000000
 PARAMETER C_FCLK_CLK2_FREQ = 50000000
 PARAMETER C_FCLK_CLK3_FREQ = 50000000
 PORT MIO = processing_system7_0_MIO
 PORT PS_SRSTB = processing_system7_0_PS_SRSTB
 PORT PS_CLK = processing_system7_0_PS_CLK
 PORT PS_PORB = processing_system7_0_PS_PORB
 PORT DDR_Clk = processing_system7_0_DDR_Clk
 PORT DDR_Clk_n = processing_system7_0_DDR_Clk_n
 PORT DDR_CKE = processing_system7_0_DDR_CKE
 PORT DDR_CS_n = processing_system7_0_DDR_CS_n
 PORT DDR_RAS_n = processing_system7_0_DDR_RAS_n
 PORT DDR_CAS_n = processing_system7_0_DDR_CAS_n
 PORT DDR_WEB = processing_system7_0_DDR_WEB
 PORT DDR_BankAddr = processing_system7_0_DDR_BankAddr
 PORT DDR_Addr = processing_system7_0_DDR_Addr
 PORT DDR_ODT = processing_system7_0_DDR_ODT
 PORT DDR_DRSTB = processing_system7_0_DDR_DRSTB
 PORT DDR_DQ = processing_system7_0_DDR_DQ
 PORT DDR_DM = processing_system7_0_DDR_DM
 PORT DDR_DQS = processing_system7_0_DDR_DQS
 PORT DDR_DQS_n = processing_system7_0_DDR_DQS_n
 PORT DDR_VRN = processing_system7_0_DDR_VRN
 PORT DDR_VRP = processing_system7_0_DDR_VRP
 PORT FCLK_CLK0 = processing_system7_0_FCLK_CLK0
END

 

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Explorer
Explorer
7,804 Views
Registered: ‎12-05-2012

Re: Connecting peripherals in XPS (EDK 14.2)

i HAVE AN other warning when I run the synthesis in planahead tool
WARNING:EDK -
C:\Programme\Xilinx\14.2\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_
i2c_v1_00_a\data\ps7_i2c_v2_1_0.mpd line 107 Unknown PORT subproperty IIC
Serial Data
WARNING:EDK -
C:\Programme\Xilinx\14.2\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_
i2c_v1_00_a\data\ps7_i2c_v2_1_0.mpd line 108 Unknown PORT subproperty IIC
Serial Clock
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Explorer
Explorer
7,802 Views
Registered: ‎12-05-2012

Re: Connecting peripherals in XPS (EDK 14.2)

This is the final error generated in the sdk when I try to implement peripheral tests
D:\Gujjeti_TEMP\thesis.sdk\SDK\SDK_Export\peripheral_tests_bsp_1\ps7_cortexa9_0\libsrc\standalone_v3_06_a\src/print.c:26: undefined reference to `outbyte'
collect2: ld returned 1 exit status
make: *** [peripheral_tests_1.elf] Fehler 1
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Explorer
Explorer
7,796 Views
Registered: ‎12-05-2012

Re: Connecting peripherals in XPS (EDK 14.2)

Can anyone provide me some documentation on how to connect the I2C to xps may be that would help me understand my problem .

 

Thanks in advance

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Visitor quame
Visitor
7,562 Views
Registered: ‎03-12-2013

Re: Connecting peripherals in XPS (EDK 14.2)

Hi,can you generate the bitstream at all(.bit file)?..or is it the image file from sdk that you cannot generate? 

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Visitor vibhuthk
Visitor
1,891 Views
Registered: ‎06-06-2014

Re: Connecting peripherals in XPS (EDK 14.2)

have you overcome this floatinf connection error, if yes how can you please tell, what could be the possible reasons for this eroor, i am getting this in this form
WARNING:EDK:4181 - PORT: Peripheral_Reset, CONNECTOR: proc_sys_reset_0_Peripheral_Reset - floating connection - C:\xps\Final_v1.mhs line 48

WARNING:EDK:4181 - PORT: FSL0_S_CLK, CONNECTOR: fsl_v0s_FSL_S_Clk - floating connection - E:\programfiles\14.7\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_50_c\data\microblaze_v2_1_0.mpd line 741
WARNING:EDK:4181 - PORT: FSL0_M_CLK, CONNECTOR: fsl_v0m_FSL_M_Clk - floating connection - E:\programfiles\14.7\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_50_c\data\microblaze_v2_1_0.mpd line 746
WARNING:EDK:4181 - PORT: FSL1_M_CLK, CONNECTOR: fsl_vcm_FSL_M_Clk - floating connection - E:\programfiles\14.7\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_50_c\data\microblaze_v2_1_0.mpd line 756
WARNING:EDK:4181 - PORT: FSL0_S_CLK, CONNECTOR: fsl_v1s_FSL_S_Clk - floating connection - E:\programfiles\14.7\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_50_c\data\microblaze_v2_1_0.mpd line 741
WARNING:EDK:4181 - PORT: FSL0_M_CLK, CONNECTOR: fsl_v1m_FSL_M_Clk - floating connection - E:\programfiles\14.7\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_50_c\data\microblaze_v2_1_0.mpd line 746
WARNING:EDK:4181 - PORT: FSL0_S_CLK, CONNECTOR: fsl_v2s_FSL_S_Clk - floating connection - E:\programfiles\14.7\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_50_c\data\microblaze_v2_1_0.mpd line 741
WARNING:EDK:4181 - PORT: FSL0_M_CLK, CONNECTOR: fsl_v2m_FSL_M_Clk - floating connection - E:\programfiles\14.7\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_50_c\data\microblaze_v2_1_0.mpd line 746
WARNING:EDK:4181 - PORT: FSL0_S_CLK, CONNECTOR: fsl_v3s_FSL_S_Clk - floating connection - E:\programfiles\14.7\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_50_c\data\microblaze_v2_1_0.mpd line 741
WARNING:EDK:4181 - PORT: FSL0_M_CLK, CONNECTOR: fsl_v3m_FSL_M_Clk - floating connection - E:\programfiles\14.7\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_50_c\data\microblaze_v2_1_0.mpd line 746
WARNING:EDK - :EDK - IPNAME: axi_7series_ddrx, INSTANCE:DDR3_SDRAM - Clock port 'freq_refclk' phase not checked because the MIG recommended value cannot be determined.

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Community Manager
Community Manager
1,881 Views
Registered: ‎06-14-2012

Re: Connecting peripherals in XPS (EDK 14.2)

Hi

This occurs if the design left a connection for non-existent peripherals. The unused connection will be safely trimmed. 

 

Otherwise please make the connections appropriately.

 

Regards

Sikta

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