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Registered: ‎02-08-2010

Constraint error in PlanAhead 13.4



I'm currently working on a project involving XPS, ISE and PlanAhead, all in 13.4.

I have an ISE design, containing an XPS project and other components.

When implementing the design using ISE, I have no problem or error, and obtain a functional bitstream that I am able to successfully test using the MicroBlaze.


But I now need to add partially reconfigurable elements to the design.

I then add the black box entity to the XPS project, synthesize the whole architecture using ISE, and then create a PlanAhead project where I import the ngc files. ncf files are automatically added to the project by PlanAhead.


I create the partially reconfigurable elements, link to the corresponding netlists previously generated using ISE, and launch the run.


But there, I obtain the following errors:


[ConstraintSystem 58] Constraint <TIMEGRP data_bus_axi_local_flops =   FFS("data_bus_axi/*")  RAMS("data_bus_axi/*" :         "data_bus_axi/*") EXCEPT  "data_bus_axi_clock_conv_slow_div2";> [bb.ucf(30)]: FFS "data_bus_axi/*" does not match any design objects.

[ConstraintSystem 58] Constraint <TIMEGRP data_bus_axi_local_flops =   FFS("data_bus_axi/*")  RAMS("data_bus_axi/*" :         "data_bus_axi/*") EXCEPT  "data_bus_axi_clock_conv_slow_div2";> [bb.ucf(30)]: RAMS "data_bus_axi/*" does not match any design objects.

[ConstraintSystem 58] Constraint <TIMEGRP data_bus_axi_local_flops =   FFS("data_bus_axi/*")  RAMS("data_bus_axi/*" :         "data_bus_axi/*") EXCEPT  "data_bus_axi_clock_conv_slow_div2";> [bb.ucf(30)]: RAMS "data_bus_axi/*" does not match any design objects.

These errors are related to an axi_interconnect component (there is another axi_interconnect in my design, that is an axi lite).

I tried comparing the error with the functional static design implemented using ISE, and I found that the tool had the same problem, but treated it as a warning instead of errors:


WARNING:ConstraintSystem:58 - Constraint <TIMEGRP data_bus_axi_local_flops =
   RAMS("system_i/data_bus_axi/data_bus_axi/*") EXCEPT
   data_bus_axi_clock_conv_slow_div2;>: RAMS
   "system_i/data_bus_axi/data_bus_axi/*" does not match any design objects.

As ISE simply ignored the constraint, I tried commenting it in the original constraint file. But this constraint file is located in the XPS project, under the implementation folder. Thus, the file is regenerated on implementation, overwriting my changes.


I see two workarounds to this:

- making PlanAhead consider ConstraintSystem:58 as a warning instead of an error,

- modifing XPS project so that the generated constraint file does not contain the wrong constraint.


Is there any way to do one of there changes? Or another way to solve this?


Thanks in advance.

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Registered: ‎02-08-2010

OK, I've finally found the -aut option (Project settings ->- Implementation -> Translate -> -aut), which description is:


Allow Unmatched Timegroups. Use this option to generate a warning rather than an error for Timegroup constraints that cannot be found in the design.

It seems to match pretty good the error I obtain, which is a timegroup constraint targetting an object that isn't found in the design.


Then, NGDBUILD is launched by PlanAhead using the following command (found in runme.log):


*** Running ngdbuild
    with args -intstyle ise -p xc6vlx240tff1759-2 -uc bb.ucf -aut bb.edf

Command Line: /opt/Xilinx/13.4/ISE_DS/ISE/bin/lin64/unwrapped/ngdbuild -intstyle
ise -p xc6vlx240tff1759-2 -uc bb.ucf -aut bb.edf

Which tends to confirm the option is taken into consideration.


But in the end... Still the same error.


Any idea?

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