04-04-201502:10 AM - last edited on 04-06-201508:09 AM by robn
Create and package IP?
hi @ all,
i m new to zynq 7030 and fpga... lem'me make it simple.. for example, i have a 8 bit adder logic in fpga section... i'm getting the bits from register A and B and storing it to regiister C... now what i want is i have to access the register C using AXI GP... what should i do??? as i m a fresher, i dont know too much technical things.. so answer this question briefly....
In Vivado, click on the top menu option "Tools", then select "Create and Package IP". From there, select "Create a new AXI 4 Peripheral". Accept the defaults, with the exception to name the IP to your liking, and select "Edit IP" on the last screen.
Once you do this, you'll see a new Vivado project open, with some 2 files. The top is simply a wrapper, but the submodule has several state machines for AXI. do a search for "slv_reg0".
The core by default will have 4 registers that can be accessed by the GP port, both read and write. Use this template to see how you can fold in your code, and instead of "slv_reg0", you can use "register C".
I'll move this to the embedded forum for more support.