UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
7,520 Views
Registered: ‎06-29-2009

Custom IP has no conected BUS2IP_DATA(0:31) for the user_logic

Jump to solution

Hi,

 

I am trying to use a custom IP in XPS for an SP601 board , but it doesn't realy work. The IP basicly has 4 registers which I would like to use to controll the ICAP.

 

When I analized the IP in ISE , I noticed that in the RTL schematic there was no connection for the Bus2IP_data(31:0) in the user logic block.  All other connections looks ok.

I searched through the VHDL code again and I don't understand why it's not connected. 

 

I only added a few things(in blue) to the XPS generated code.  I never tried to use a custom IP before, so I guess there is something I forgot to do?

As I actualy understood: I don't have to add any code to get data from the BUS to the registers in the IP, this should automaticly be done by the processes SLAVE_REG_WRITE_PROC and SLAVE_REG_READ_PROC,is that correct?

 

 

Serge

 

 

 

 

The USER_LOGIC code:  (I didn't change any other vhdl file)

 

------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.            **
-- **                                                                       **
-- ** Xilinx, Inc.                                                          **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"         **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND       **
-- ** SOLUTIONS FOR XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE,        **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,        **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION           **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,     **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE      **
-- ** FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY              **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE               **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR        **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF       **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS       **
-- ** FOR A PARTICULAR PURPOSE.                                             **
-- **                                                                       **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename:          user_logic.vhd
-- Version:           1.00.a
-- Description:       User logic.
-- Date:              Mon Feb 22 13:25:15 2010 (by Create and Import Peripheral Wizard)
-- VHDL Standard:     VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
--   active low signals:                    "*_n"
--   clock signals:                         "clk", "clk_div#", "clk_#x"
--   reset signals:                         "rst", "rst_n"
--   generics:                              "C_*"
--   user defined types:                    "*_TYPE"
--   state machine next state:              "*_ns"
--   state machine current state:           "*_cs"
--   combinatorial signals:                 "*_com"
--   pipelined or register delay signals:   "*_d#"
--   counter signals:                       "*cnt*"
--   clock enable signals:                  "*_ce"
--   internal version of output port:       "*_i"
--   device pins:                           "*_pin"
--   ports:                                 "- Names begin with Uppercase"
--   processes:                             "*_PROCESS"
--   component instantiations:              "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------

-- DO NOT EDIT BELOW THIS LINE --------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;

-- DO NOT EDIT ABOVE THIS LINE --------------------

--USER libraries added here

------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
--   C_SLV_DWIDTH                 -- Slave interface data bus width
--   C_NUM_REG                    -- Number of software accessible registers
--
-- Definition of Ports:
--   Bus2IP_Clk                   -- Bus to IP clock
--   Bus2IP_Reset                 -- Bus to IP reset
--   Bus2IP_Data                  -- Bus to IP data bus
--   Bus2IP_BE                    -- Bus to IP byte enables
--   Bus2IP_RdCE                  -- Bus to IP read chip enable
--   Bus2IP_WrCE                  -- Bus to IP write chip enable
--   IP2Bus_Data                  -- IP to Bus data bus
--   IP2Bus_RdAck                 -- IP to Bus read transfer acknowledgement
--   IP2Bus_WrAck                 -- IP to Bus write transfer acknowledgement
--   IP2Bus_Error                 -- IP to Bus error response
------------------------------------------------------------------------------

entity user_logic is
  generic
  (
    -- ADD USER GENERICS BELOW THIS LINE ---------------
    --USER generics added here
    -- ADD USER GENERICS ABOVE THIS LINE ---------------

    -- DO NOT EDIT BELOW THIS LINE ---------------------
    -- Bus protocol parameters, do not add to or delete
    C_SLV_DWIDTH                   : integer              := 32;
    C_NUM_REG                      : integer              := 4
    -- DO NOT EDIT ABOVE THIS LINE ---------------------
  );
  port
  (
    -- ADD USER PORTS BELOW THIS LINE ------------------
    --USER ports added here
    -- ADD USER PORTS ABOVE THIS LINE ------------------

    -- DO NOT EDIT BELOW THIS LINE ---------------------
    -- Bus protocol ports, do not add to or delete
    Bus2IP_Clk                     : in  std_logic;
    Bus2IP_Reset                   : in  std_logic;
    Bus2IP_Data                    : in  std_logic_vector(0 to C_SLV_DWIDTH-1);
    Bus2IP_BE                      : in  std_logic_vector(0 to C_SLV_DWIDTH/8-1);
    Bus2IP_RdCE                    : in  std_logic_vector(0 to C_NUM_REG-1);
    Bus2IP_WrCE                    : in  std_logic_vector(0 to C_NUM_REG-1);
    IP2Bus_Data                    : out std_logic_vector(0 to C_SLV_DWIDTH-1);
    IP2Bus_RdAck                   : out std_logic;
    IP2Bus_WrAck                   : out std_logic;
    IP2Bus_Error                   : out std_logic
    -- DO NOT EDIT ABOVE THIS LINE ---------------------
  );

  attribute SIGIS : string;
  attribute SIGIS of Bus2IP_Clk    : signal is "CLK";
  attribute SIGIS of Bus2IP_Reset  : signal is "RST";

end entity user_logic;

------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------

architecture IMP of user_logic is

  --USER signal declarations added here, as needed for user logic

  ------------------------------------------
  -- Signals for user logic slave model s/w accessible register example
  ------------------------------------------
  signal slv_reg0                       : std_logic_vector(0 to C_SLV_DWIDTH-1);
  signal slv_reg1                       : std_logic_vector(0 to C_SLV_DWIDTH-1);
  signal slv_reg2                       : std_logic_vector(0 to C_SLV_DWIDTH-1);
  signal slv_reg3                       : std_logic_vector(0 to C_SLV_DWIDTH-1);
  signal slv_reg_write_sel              : std_logic_vector(0 to 3);
  signal slv_reg_read_sel               : std_logic_vector(0 to 3);
  signal slv_ip2bus_data                : std_logic_vector(0 to C_SLV_DWIDTH-1);
  signal slv_read_ack                   : std_logic;
  signal slv_write_ack                  : std_logic;
  signal icapOut                        : std_logic_vector(15 downto 0);
  signal icapIn                         : std_logic_vector(15 downto 0);
  signal icapWrite                      : std_logic;
  signal icapClk                           : std_logic;
  signal icapCE                         : std_logic;
  signal icapBusy                          : std_logic;
 
 
 
 
 
component icap_spartan6
port (
   BUSY : out std_logic;   -- 1-bit Busy output
   O : out std_logic_vector(15 downto 0);         -- 16-bit Configuartion data output bus
   CE : in std_logic;       -- 1-bit Active low clock enable input
   CLK : in std_logic;     -- 1-bit Clock input
   I : in std_logic_vector(15 downto 0);         -- 16-bit Configuration data input bus
   WRITE : in std_logic);
end component;

   

begin



    ---instance of ICAP6
    ---------------------------

ICAP_SPARTAN6_inst : icap_spartan6
port map (
   BUSY => icapBusy,   -- 1-bit Busy output
 
    O(15) => icapOut(15),         -- 16-bit Configuartion data output bus
    O(14) => icapOut(14),         -- 16-bit Configuartion data output bus
    O(13) => icapOut(13),         -- 16-bit Configuartion data output bus
    O(12) => icapOut(12),         -- 16-bit Configuartion data output bus
    O(11) => icapOut(11),         -- 16-bit Configuartion data output bus
    O(10) => icapOut(10),         -- 16-bit Configuartion data output bus
    O(9) => icapOut(9),         -- 16-bit Configuartion data output bus
    O(8) => icapOut(8),         -- 16-bit Configuartion data output bus
    O(7) => icapOut(7),         -- 16-bit Configuartion data output bus
    O(6) => icapOut(6),         -- 16-bit Configuartion data output bus
    O(5) => icapOut(5),         -- 16-bit Configuartion data output bus
    O(4) => icapOut(4),         -- 16-bit Configuartion data output bus
    O(3) => icapOut(3),         -- 16-bit Configuartion data output bus
    O(2) => icapOut(2),         -- 16-bit Configuartion data output bus
    O(1) => icapOut(1),         -- 16-bit Configuartion data output bus
    O(0) => icapOut(0),         -- 16-bit Configuartion data output bus


    CE => icapCE,       -- 1-bit Active low clock enable input
   CLK => icapCLK,     -- 1-bit Clock input
  
   I(15) => icapIn(8),         -- 16-bit Configuration data input bus
   I(14) => icapIn(9),         -- 16-bit Configuration data input bus
   I(13) => icapIn(10),         -- 16-bit Configuration data input bus
   I(12) => icapIn(11),         -- 16-bit Configuration data input bus
   I(11) => icapIn(12),         -- 16-bit Configuration data input bus
   I(10) => icapIn(13),         -- 16-bit Configuration data input bus
   I(9) => icapIn(14),         -- 16-bit Configuration data input bus
   I(8) => icapIn(15),         -- 16-bit Configuration data input bus
   I(7) => icapIn(0),         -- 16-bit Configuration data input bus
   I(6) => icapIn(1),         -- 16-bit Configuration data input bus
   I(5) => icapIn(2),         -- 16-bit Configuration data input bus
   I(4) => icapIn(3),         -- 16-bit Configuration data input bus
   I(3) => icapIn(4),         -- 16-bit Configuration data input bus
   I(2) => icapIn(5),         -- 16-bit Configuration data input bus
   I(1) => icapIn(6),         -- 16-bit Configuration data input bus
   I(0) => icapIn(7),         -- 16-bit Configuration data input bus
  
   WRITE => icapWrite  -- 1-bit Active low write input
);




  --USER logic implementation added here

  ------------------------------------------
  -- Example code to read/write user logic slave model s/w accessible registers
  --
  -- Note:
  -- The example code presented here is to show you one way of reading/writing
  -- software accessible registers implemented in the user logic slave model.
  -- Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond
  -- to one software accessible register by the top level template. For example,
  -- if you have four 32 bit software accessible registers in the user logic,
  -- you are basically operating on the following memory mapped registers:
  --
  --    Bus2IP_WrCE/Bus2IP_RdCE   Memory Mapped Register
  --                     "1000"   C_BASEADDR + 0x0
  --                     "0100"   C_BASEADDR + 0x4
  --                     "0010"   C_BASEADDR + 0x8
  --                     "0001"   C_BASEADDR + 0xC
  --
  ------------------------------------------
  slv_reg_write_sel <= Bus2IP_WrCE(0 to 3);
  slv_reg_read_sel  <= Bus2IP_RdCE(0 to 3);
  slv_write_ack     <= Bus2IP_WrCE(0) or Bus2IP_WrCE(1) or Bus2IP_WrCE(2) or Bus2IP_WrCE(3);
  slv_read_ack      <= Bus2IP_RdCE(0) or Bus2IP_RdCE(1) or Bus2IP_RdCE(2) or Bus2IP_RdCE(3);

  -- implement slave model software accessible register(s)
  SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is
  begin

    if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
      if Bus2IP_Reset = '1' then
        slv_reg0 <= (others => '0');
        slv_reg1 <= (others => '0');
        slv_reg2 <= (others => '0');
        slv_reg3 <= (others => '0');
      else
        case slv_reg_write_sel is
          when "1000" =>
            for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
              if ( Bus2IP_BE(byte_index) = '1' ) then
                slv_reg0(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
              end if;
            end loop;
                ---Pass the value of REG_0
                icapWrite <= slv_reg0(0);
                icapClk <= slv_reg0(1);
                icapCE <= slv_reg0(2);
               

               
          when "0100" =>
            for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
              if ( Bus2IP_BE(byte_index) = '1' ) then
                slv_reg1(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
              end if;
            end loop;
          when "0010" =>
            for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
              if ( Bus2IP_BE(byte_index) = '1' ) then
                slv_reg2(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
              end if;
            end loop;
                --- Pass the value of reg3
                icapIn(15) <= slv_reg2(8);
                icapIn(14) <= slv_reg2(9);
                icapIn(13) <= slv_reg2(10);
                icapIn(12) <= slv_reg2(11);
                icapIn(11) <= slv_reg2(12);
                icapIn(10) <= slv_reg2(13);
                icapIn(9) <= slv_reg2(14);
                icapIn(8) <= slv_reg2(15);
                icapIn(7) <= slv_reg2(0);
                icapIn(6) <= slv_reg2(1);
                icapIn(5) <= slv_reg2(2);
                icapIn(4) <= slv_reg2(3);
                icapIn(3) <= slv_reg2(4);
                icapIn(2) <= slv_reg2(5);
                icapIn(1) <= slv_reg2(6);
                icapIn(0) <= slv_reg2(7);
               

          when "0001" =>
            for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
              if ( Bus2IP_BE(byte_index) = '1' ) then
                slv_reg3(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
              end if;
            end loop;
          when others => null;
        end case;
      end if;
    end if;

  end process SLAVE_REG_WRITE_PROC;

  -- implement slave model software accessible register(s) read mux
  SLAVE_REG_READ_PROC : process( slv_reg_read_sel, slv_reg0, slv_reg1, slv_reg2, slv_reg3 ) is
  begin

    --  pass the data to be send to MB
    slv_reg3(15) <= icapOut(15);
    slv_reg3(14) <= icapOut(14);
    slv_reg3(13) <= icapOut(13);
    slv_reg3(12) <= icapOut(12);
    slv_reg3(11) <= icapOut(11);
    slv_reg3(10) <= icapOut(10);
    slv_reg3(9) <= icapOut(9);
    slv_reg3(8) <= icapOut(8);
    slv_reg3(7) <= icapOut(7);
    slv_reg3(6) <= icapOut(6);
    slv_reg3(5) <= icapOut(5);
    slv_reg3(4) <= icapOut(4);
    slv_reg3(3) <= icapOut(3);
    slv_reg3(2) <= icapOut(2);
    slv_reg3(1) <= icapOut(1);
    slv_reg3(0) <= icapOut(0);
   
   
    slv_reg1(0) <= icapBusy;

   
   
   

    case slv_reg_read_sel is
      when "1000" => slv_ip2bus_data <= slv_reg0;
      when "0100" => slv_ip2bus_data <= slv_reg1;
      when "0010" => slv_ip2bus_data <= slv_reg2;
      when "0001" => slv_ip2bus_data <= slv_reg3;
      when others => slv_ip2bus_data <= (others => '0');
    end case;

  end process SLAVE_REG_READ_PROC;

  ------------------------------------------
  -- Example code to drive IP to Bus signals
  ------------------------------------------
  IP2Bus_Data  <= slv_ip2bus_data when slv_read_ack = '1' else
                  (others => '0');

  IP2Bus_WrAck <= slv_write_ack;
  IP2Bus_RdAck <= slv_read_ack;
  IP2Bus_Error <= '0';

end IMP;
 

Tags (4)
0 Kudos
1 Solution

Accepted Solutions
9,483 Views
Registered: ‎06-29-2009

Re: Custom IP has no conected BUS2IP_DATA(0:31) for the user_logic

Jump to solution

After some test, the next conclusion has been made:

 

  -  The connection is actualy made ,  but it is just not drawed in the RTL schematic.

 

Serge

 

Message Edited by serge.kubera@ehb.be on 03-03-2010 04:11 PM
0 Kudos
5 Replies
Adventurer
Adventurer
7,515 Views
Registered: ‎01-28-2008

Re: Custom IP has no conected BUS2IP_DATA(0:31) for the user_logic

Jump to solution

One possibility is you did not connect your component to the PLB after you instantiated (or you didn't set/generate the address for the IP Core).  Can you include your MHS File (or at least the snippet where you code is instantiated in the project).

0 Kudos
Explorer
Explorer
7,507 Views
Registered: ‎01-09-2009

Re: Custom IP has no conected BUS2IP_DATA(0:31) for the user_logic

Jump to solution

you are making a couple of mistakes. The code below is a good exmaple for your case. I have tested it, and it worked well. I used registers 6 and 7 to send commands and data from the processor to the IP, while other registers(Reg0 to 5) are used to send data and status info from the IP to the processor.

 

 

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; library proc_common_v2_00_a; use proc_common_v2_00_a.proc_common_pkg.all; entity user_logic is generic ( C_SLV_DWIDTH : integer := 32; C_NUM_REG : integer := 8 ); port ( clk40 : in std_logic; lff : in std_logic; lrl : in std_logic_vector (3 downto 0); ldown : in std_logic; lsf : in std_logic_vector(3 downto 0); ud : out std_logic_vector(63 downto 0); ureset : out std_logic; utest : out std_logic; udw : out std_logic_vector(1 downto 0); uctrl : out std_logic; uwen : out std_logic; uclk : out std_logic; usf : out std_logic_vector(3 downto 0); Bus2IP_Clk : in std_logic; Bus2IP_Reset : in std_logic; Bus2IP_Data : in std_logic_vector(0 to C_SLV_DWIDTH-1); Bus2IP_BE : in std_logic_vector(0 to C_SLV_DWIDTH/8-1); Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_REG-1); Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_REG-1); IP2Bus_Data : out std_logic_vector(0 to C_SLV_DWIDTH-1); IP2Bus_RdAck : out std_logic; IP2Bus_WrAck : out std_logic; IP2Bus_Error : out std_logic ); attribute SIGIS : string; attribute SIGIS of Bus2IP_Clk : signal is "CLK"; attribute SIGIS of Bus2IP_Reset : signal is "RST"; end entity user_logic; ------------------------------------------------------------------------------ -- Architecture section ------------------------------------------------------------------------------ architecture IMP of user_logic is --USER signal declarations added here, as needed for user logic signal ud_1 : std_logic_vector(63 downto 0); signal ureset_1 : std_logic; signal utest_1 : std_logic; signal udw_1 : std_logic_vector(1 downto 0); signal uctrl_1 : std_logic; signal uwen_1 : std_logic; signal state_1 : std_logic_vector(5 downto 0); signal crc_inspect_1 : std_logic_vector(15 downto 0); signal lff_1 : std_logic; signal lrl_1 : std_logic_vector(3 downto 0); signal ldown_1 : std_logic; component custom_ip port ( clk : in std_logic; rst : in std_logic; start : in std_logic; stop : in std_logic; reset : in std_logic; test_mode : in std_logic; clk40 : in std_logic; data_count : in std_logic_vector(31 downto 0); lff : in std_logic; lrl : in std_logic_vector (3 downto 0); ldown : in std_logic; lsf : in std_logic_vector(3 downto 0); ud : out std_logic_vector(63 downto 0); ureset : out std_logic; utest : out std_logic; udw : out std_logic_vector(1 downto 0); uctrl : out std_logic; uwen : out std_logic; uclk : out std_logic; usf : out std_logic_vector(3 downto 0); state_debug : out std_logic_vector(5 downto 0); crc_inspect : out std_logic_vector(15 downto 0); lff_debug : out std_logic; lrl_debug : out std_logic_vector(3 downto 0); ldown_debug : out std_logic ); end component; ------------------------------------------ -- Signals for user logic slave model s/w accessible register example ------------------------------------------ signal slv_reg0 : std_logic_vector(0 to C_SLV_DWIDTH-1); signal slv_reg1 : std_logic_vector(0 to C_SLV_DWIDTH-1); signal slv_reg2 : std_logic_vector(0 to C_SLV_DWIDTH-1); signal slv_reg3 : std_logic_vector(0 to C_SLV_DWIDTH-1); signal slv_reg4 : std_logic_vector(0 to C_SLV_DWIDTH-1); signal slv_reg5 : std_logic_vector(0 to C_SLV_DWIDTH-1); signal slv_reg6 : std_logic_vector(0 to C_SLV_DWIDTH-1); signal slv_reg7 : std_logic_vector(0 to C_SLV_DWIDTH-1); signal slv_reg_write_sel : std_logic_vector(0 to 7); signal slv_reg_read_sel : std_logic_vector(0 to 7); signal slv_ip2bus_data : std_logic_vector(0 to C_SLV_DWIDTH-1); signal slv_read_ack : std_logic; signal slv_write_ack : std_logic; begin --USER logic implementation added here ud <= ud_1; ureset <= ureset_1; utest <= utest_1; udw <= udw_1; uctrl <= uctrl_1; uwen <= uwen_1; custom_ip_0 : custom_ip port map ( clk => Bus2IP_Clk, rst => Bus2IP_Reset, start => slv_reg7(31), stop => slv_reg7(30), reset => slv_reg7(29), test_mode => slv_reg7(28), clk40 => clk40, data_count => slv_reg6, lff => lff, lrl => lrl, ldown => ldown, lsf => lsf, ud => ud_1, ureset => ureset_1, utest => utest_1, udw => udw_1, uctrl => uctrl_1, uwen => uwen_1, uclk => uclk, usf => usf, state_debug => state_1, crc_inspect => crc_inspect_1, lff_debug => lff_1, lrl_debug => lrl_1, ldown_debug => ldown_1 ); slv_reg_write_sel <= Bus2IP_WrCE(0 to 7); slv_reg_read_sel <= Bus2IP_RdCE(0 to 7); slv_write_ack <= Bus2IP_WrCE(0) or Bus2IP_WrCE(1) or Bus2IP_WrCE(2) or Bus2IP_WrCE(3) or Bus2IP_WrCE(4) or Bus2IP_WrCE(5) or Bus2IP_WrCE(6) or Bus2IP_WrCE(7); slv_read_ack <= Bus2IP_RdCE(0) or Bus2IP_RdCE(1) or Bus2IP_RdCE(2) or Bus2IP_RdCE(3) or Bus2IP_RdCE(4) or Bus2IP_RdCE(5) or Bus2IP_RdCE(6) or Bus2IP_RdCE(7); -- implement slave model software accessible register(s) SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is begin if Bus2IP_Clk'event and Bus2IP_Clk = '1' then if Bus2IP_Reset = '1' then slv_reg0 <= (others => '0'); slv_reg1 <= (others => '0'); slv_reg2 <= (others => '0'); slv_reg3 <= (others => '0'); slv_reg4 <= (others => '0'); slv_reg5 <= (others => '0'); slv_reg6 <= (others => '0'); slv_reg7 <= (others => '0'); else case slv_reg_write_sel is when "10000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg0(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7); end if; end loop; when "01000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg1(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7); end if; end loop; when "00100000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg2(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7); end if; end loop; when "00010000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg3(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7); end if; end loop; when "00001000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg4(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7); end if; end loop; when "00000100" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg5(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7); end if; end loop; when "00000010" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg6(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7); end if; end loop; when "00000001" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg7(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7); end if; end loop; when others => null; end case; end if; end if; end process SLAVE_REG_WRITE_PROC; -- implement slave model software accessible register(s) read mux SLAVE_REG_READ_PROC : process( slv_reg_read_sel, slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7 ) is begin case slv_reg_read_sel is when "10000000" => slv_ip2bus_data <= ud_1(31 downto 0); when "01000000" => slv_ip2bus_data <= ud_1(63 downto 32); when "00100000" => slv_ip2bus_data(26 to 31) <= state_1; slv_ip2bus_data(0 to 25) <= (others => '0'); when "00010000" => slv_ip2bus_data(31) <= ureset_1; slv_ip2bus_data(30) <= utest_1; slv_ip2bus_data(29) <= uctrl_1; slv_ip2bus_data(28) <= uwen_1; slv_ip2bus_data(26 to 27) <= udw_1; slv_ip2bus_data(0 to 25) <= (others => '0'); when "00001000" => slv_ip2bus_data(28 to 31) <= lrl_1; slv_ip2bus_data(27) <= lff_1; slv_ip2bus_data(26) <= ldown_1; slv_ip2bus_data(0 to 25) <= (others => '0'); when "00000100" => slv_ip2bus_data(16 to 31) <= crc_inspect_1; slv_ip2bus_data(0 to 15) <= (others => '0'); when "00000010" => slv_ip2bus_data <= slv_reg6; when others => slv_ip2bus_data <= (others => '0'); end case; end process SLAVE_REG_READ_PROC; IP2Bus_Data <= slv_ip2bus_data when slv_read_ack = '1' else (others => '0'); IP2Bus_WrAck <= slv_write_ack; IP2Bus_RdAck <= slv_read_ack; IP2Bus_Error <= '0'; end IMP;

 

 

 

0 Kudos
7,469 Views
Registered: ‎06-29-2009

Re: Custom IP has no conected BUS2IP_DATA(0:31) for the user_logic

Jump to solution

Thanx for reply.   I controled the bus ... and I connected it (looks like).

 

I think that's the snippet you would need?


BEGIN demoip
 PARAMETER INSTANCE = demoip_0
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_BASEADDR = 0xc1000000
 PARAMETER C_HIGHADDR = 0xc100ffff
 BUS_INTERFACE SPLB = mb_plb
END

 

 

 

The entire MHS file follows here:


# ########################################################################
# Copyright(C) 2009 by Xilinx, Inc. All rights reserved.               ##
# ##
# You may copy and modify these files for your own internal use solely ##
# with Xilinx programmable logic devices and  Xilinx EDK system or     ##
# create IP modules solely for Xilinx programmable logic devices and   ##
# Xilinx EDK system. No rights are granted to distribute any files     ##
# unless they are distributed in Xilinx programmable logic devices.    ##
# ##
# Source code is provided  as-is , with no obligation on the part of   ##
# Xilinx to provide support.                                           ##
# ##
# #########################################################################
# ############################################################################
# ##
# Spartan-6 MicroBlaze BIST Reference System                               ##
# Xilinx EDK 11.4 ISE 11.4                                                 ##
# ##
# ##
# Target Board: Xilinx Spartan-6 SP601 Evaluation Platform Rev C           ##
# Family:    spartan6                                                      ##
# Device:    xc6slx16                                                      ##
# Package:   csg324                                                        ##
# Speed Grade:   -2                                                        ##
# ##
# Processor: MicroBlaze                                                    ##
# Processor clock frequency: 95.238095 MHz                                 ##
# Bus clock frequency: 95.238095 MHz                                       ##
# Debug interface: FPGA JTAG                                               ##
# On Chip Memory :   40 KB                                                 ##
# Total Off Chip Memory :  144 MB                                          ##
# - DDR2_SDRAM =  128 MB                                                   ##
# - FLASH = 16 MB                                                          ##
# ##
# ############################################################################
 PARAMETER VERSION = 2.1.0


# Uart
 PORT fpga_0_RS232_Uart_1_sin_pin = fpga_0_RS232_Uart_1_sin, DIR = I
 PORT fpga_0_RS232_Uart_1_sout_pin = fpga_0_RS232_Uart_1_sout, DIR = O
# LEDs
 PORT fpga_0_LEDs_8Bit_GPIO_d_out_pin = fpga_0_LEDs_8Bit_GPIO_d_out, DIR = O, VEC = [0:3]
# Push Buttons
 PORT fpga_0_Push_Buttons_4Bit_GPIO_IO_pin = fpga_0_Push_Buttons_4Bit_GPIO_IO, DIR = IO, VEC = [0:3]
# Dip Switches
 PORT fpga_0_DIP_Switches_4Bit_GPIO_IO_I_pin = fpga_0_DIP_Switches_4Bit_GPIO_IO_I_pin, DIR = I, VEC = [0:3]
# Flash
 PORT FLASH_24 = net_gnd, DIR = O
 PORT fpga_0_FLASH_Mem_A_pin = fpga_0_FLASH_Mem_A, DIR = O, VEC = [8:31]
 PORT fpga_0_FLASH_Mem_DQ_Shared_pin = fpga_0_FLASH_Mem_DQ_Shared, DIR = IO, VEC = [0:7]
 PORT fpga_0_FLASH_Mem_WEN_pin = fpga_0_FLASH_Mem_WEN, DIR = O
 PORT fpga_0_FLASH_Mem_RPN_pin = fpga_0_FLASH_Mem_RPN, DIR = O
 PORT fpga_0_FLASH_Mem_OEN_pin = fpga_0_FLASH_Mem_OEN, DIR = O
 PORT fpga_0_FLASH_Mem_CEN_pin = fpga_0_FLASH_Mem_CEN, DIR = O
# SPI Flash
 PORT fpga_0_SPI_FLASH_MOSI_pin = fpga_0_SPI_FLASH_MOSI, DIR = IO
 PORT fpga_0_SPI_FLASH_SCK_pin = fpga_0_SPI_FLASH_SCK, DIR = IO
 PORT fpga_0_SPI_FLASH_SS_pin = fpga_0_SPI_FLASH_SS, DIR = IO, VEC = [0:0]
# IIC
 PORT fpga_0_IIC_EEPROM_Scl_pin = fpga_0_IIC_EEPROM_Scl, DIR = IO
 PORT fpga_0_IIC_EEPROM_Sda_pin = fpga_0_IIC_EEPROM_Sda, DIR = IO
# DDR2
 PORT MPMC_0_mcbx_dram_addr_pin = MPMC_0_mcbx_dram_addr, DIR = O, VEC = [12:0]
 PORT MPMC_0_mcbx_dram_ba_pin = MPMC_0_mcbx_dram_ba, DIR = O, VEC = [2:0]
 PORT MPMC_0_mcbx_dram_ras_n_pin = MPMC_0_mcbx_dram_ras_n, DIR = O
 PORT MPMC_0_mcbx_dram_cas_n_pin = MPMC_0_mcbx_dram_cas_n, DIR = O
 PORT MPMC_0_mcbx_dram_we_n_pin = MPMC_0_mcbx_dram_we_n, DIR = O
 PORT MPMC_0_mcbx_dram_cke_pin = MPMC_0_mcbx_dram_cke, DIR = O
 PORT MPMC_0_mcbx_dram_clk_pin = MPMC_0_mcbx_dram_clk, DIR = O, SIGIS = CLK
 PORT MPMC_0_mcbx_dram_clk_n_pin = MPMC_0_mcbx_dram_clk_n, DIR = O, SIGIS = CLK
 PORT MPMC_0_mcbx_dram_dq = MPMC_0_mcbx_dram_dq, DIR = IO, VEC = [15:0]
 PORT MPMC_0_mcbx_dram_dqs = MPMC_0_mcbx_dram_dqs, DIR = IO
 PORT MPMC_0_mcbx_dram_udqs = MPMC_0_mcbx_dram_udqs, DIR = IO
 PORT MPMC_0_mcbx_dram_odt_pin = MPMC_0_mcbx_dram_odt, DIR = O
 PORT MPMC_0_mcbx_dram_ldm_pin = MPMC_0_mcbx_dram_ldm, DIR = O
 PORT MPMC_0_mcbx_dram_udm_pin = MPMC_0_mcbx_dram_udm, DIR = O
 PORT MPMC_0_mcbx_dram_udqs_n = MPMC_0_mcbx_dram_udqs_n, DIR = IO
 PORT MPMC_0_mcbx_dram_dqs_n = MPMC_0_mcbx_dram_dqs_n, DIR = IO
 PORT MPMC_0_mcbx_dram_rzq = MPMC_0_mcbx_dram_rzq, DIR = IO
 PORT MPMC_0_mcbx_dram_zio = MPMC_0_mcbx_dram_zio, DIR = IO
# Ethernet
 PORT fpga_0_Ethernet_MAC_PHY_tx_clk_pin = fpga_0_Ethernet_MAC_PHY_tx_clk_pin, DIR = I
 PORT fpga_0_Ethernet_MAC_PHY_rx_clk_pin = fpga_0_Ethernet_MAC_PHY_rx_clk_pin, DIR = I
 PORT fpga_0_Ethernet_MAC_PHY_crs_pin = fpga_0_Ethernet_MAC_PHY_crs_pin, DIR = I
 PORT fpga_0_Ethernet_MAC_PHY_dv_pin = fpga_0_Ethernet_MAC_PHY_dv_pin, DIR = I
 PORT fpga_0_Ethernet_MAC_PHY_rx_data_pin = fpga_0_Ethernet_MAC_PHY_rx_data_pin, DIR = I, VEC = [3:0]
 PORT fpga_0_Ethernet_MAC_PHY_col_pin = fpga_0_Ethernet_MAC_PHY_col_pin, DIR = I
 PORT fpga_0_Ethernet_MAC_PHY_rx_er_pin = fpga_0_Ethernet_MAC_PHY_rx_er_pin, DIR = I
 PORT fpga_0_Ethernet_MAC_PHY_rst_n_pin = fpga_0_Ethernet_MAC_PHY_rst_n_pin, DIR = O
 PORT fpga_0_Ethernet_MAC_PHY_tx_en_pin = fpga_0_Ethernet_MAC_PHY_tx_en_pin, DIR = O
 PORT fpga_0_Ethernet_MAC_PHY_tx_data_pin = fpga_0_Ethernet_MAC_PHY_tx_data_pin, DIR = O, VEC = [3:0]
 PORT fpga_0_Ethernet_MAC_PHY_MDC_pin = fpga_0_Ethernet_MAC_PHY_MDC_pin, DIR = O
 PORT fpga_0_Ethernet_MAC_PHY_MDIO_pin = fpga_0_Ethernet_MAC_PHY_MDIO_pin, DIR = IO
# Clocking and Reset
 PORT sys_clk_in_p = dcm_clk_s, DIR = I, DIFFERENTIAL_POLARITY = P, CLK_FREQ = 200000000, SIGIS = CLK
 PORT sys_clk_in_n = dcm_clk_s, DIR = I, DIFFERENTIAL_POLARITY = N, CLK_FREQ = 200000000, SIGIS = CLK
 PORT sys_rst_pin = sys_rst_s, DIR = I, RST_POLARITY = 1, SIGIS = RST


BEGIN mdm
 PARAMETER INSTANCE = Debug_Module
 PARAMETER HW_VER = 1.00.g
 PARAMETER C_MB_DBG_PORTS = 1
 PARAMETER C_USE_UART = 1
 PARAMETER C_UART_WIDTH = 8
 PARAMETER C_BASEADDR = 0x84400000
 PARAMETER C_HIGHADDR = 0x8440ffff
 BUS_INTERFACE SPLB = mb_plb
 BUS_INTERFACE MBDEBUG_0 = microblaze_0_dbg
 PORT Debug_SYS_Rst = Debug_SYS_Rst
END

BEGIN microblaze
 PARAMETER HW_VER = 7.20.d
 PARAMETER INSTANCE = microblaze_0
 PARAMETER C_FAMILY = spartan6
 PARAMETER C_INSTANCE = microblaze_0
 PARAMETER C_DEBUG_ENABLED = 1
 PARAMETER C_USE_ICACHE = 1
 PARAMETER C_ICACHE_BASEADDR = 0xc8000000
 PARAMETER C_ICACHE_HIGHADDR = 0xcfffffff
 PARAMETER C_CACHE_BYTE_SIZE = 2048
 PARAMETER C_ICACHE_ALWAYS_USED = 1
 PARAMETER C_USE_DCACHE = 1
 PARAMETER C_DCACHE_BASEADDR = 0xc8000000
 PARAMETER C_DCACHE_HIGHADDR = 0xcfffffff
 PARAMETER C_DCACHE_BYTE_SIZE = 2048
 PARAMETER C_DCACHE_ALWAYS_USED = 1
 BUS_INTERFACE DPLB = mb_plb
 BUS_INTERFACE IPLB = mb_plb
 BUS_INTERFACE DLMB = dlmb
 BUS_INTERFACE ILMB = ilmb
 BUS_INTERFACE DXCL = microblaze_0_DXCL
 BUS_INTERFACE IXCL = microblaze_0_IXCL
 BUS_INTERFACE DEBUG = microblaze_0_dbg
 PORT MB_RESET = mb_reset
 PORT Interrupt = Interrupt
END

BEGIN plb_v46
 PARAMETER INSTANCE = mb_plb
 PARAMETER HW_VER = 1.04.a
 PORT PLB_Clk = sys_clk_s
 PORT SYS_Rst = sys_bus_reset
END

BEGIN lmb_v10
 PARAMETER INSTANCE = ilmb
 PARAMETER HW_VER = 1.00.a
 PORT LMB_Clk = sys_clk_s
 PORT SYS_Rst = sys_bus_reset
END

BEGIN lmb_v10
 PARAMETER INSTANCE = dlmb
 PARAMETER HW_VER = 1.00.a
 PORT LMB_Clk = sys_clk_s
 PORT SYS_Rst = sys_bus_reset
END

BEGIN lmb_bram_if_cntlr
 PARAMETER INSTANCE = LocalMemory_Cntlr_D
 PARAMETER HW_VER = 2.10.b
 PARAMETER C_BASEADDR = 0x00000000
 PARAMETER C_HIGHADDR = 0x00003FFF
 BUS_INTERFACE SLMB = dlmb
 BUS_INTERFACE BRAM_PORT = dlmb_port
END

BEGIN lmb_bram_if_cntlr
 PARAMETER INSTANCE = LocalMemory_Cntlr_I
 PARAMETER HW_VER = 2.10.b
 PARAMETER C_BASEADDR = 0x00000000
 PARAMETER C_HIGHADDR = 0x00003FFF
 BUS_INTERFACE SLMB = ilmb
 BUS_INTERFACE BRAM_PORT = ilmb_port
END

BEGIN bram_block
 PARAMETER INSTANCE = lmb_bram
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE PORTA = ilmb_port
 BUS_INTERFACE PORTB = dlmb_port
END

BEGIN xps_bram_if_cntlr
 PARAMETER INSTANCE = Internal_BRAM
 PARAMETER HW_VER = 1.00.b
 PARAMETER C_SPLB_NATIVE_DWIDTH = 32
 PARAMETER C_BASEADDR = 0xc3008000
 PARAMETER C_HIGHADDR = 0xc300ffff
 BUS_INTERFACE SPLB = mb_plb
 BUS_INTERFACE PORTA = Internal_BRAM_port
END

BEGIN bram_block
 PARAMETER INSTANCE = xps_bram_if_cntlr_1_bram
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE PORTA = Internal_BRAM_port
END

BEGIN xps_uart16550
 PARAMETER INSTANCE = RS232_Uart_1
 PARAMETER HW_VER = 3.00.a
 PARAMETER C_IS_A_16550 = 1
 PARAMETER C_BASEADDR = 0x84000000
 PARAMETER C_HIGHADDR = 0x8400ffff
 BUS_INTERFACE SPLB = mb_plb
 PORT sin = fpga_0_RS232_Uart_1_sin
 PORT sout = fpga_0_RS232_Uart_1_sout
 PORT IP2INTC_Irpt = RS232_Uart_1_IP2INTC_Irpt
END

BEGIN xps_gpio
 PARAMETER INSTANCE = LEDs_8Bit
 PARAMETER HW_VER = 2.00.a
 PARAMETER C_ALL_INPUTS = 0
 PARAMETER C_GPIO_WIDTH = 4
 PARAMETER C_IS_DUAL = 0
 PARAMETER C_BASEADDR = 0x81420000
 PARAMETER C_HIGHADDR = 0x8142ffff
 BUS_INTERFACE SPLB = mb_plb
 PORT GPIO_IO_O = fpga_0_LEDs_8Bit_GPIO_d_out
END

BEGIN xps_gpio
 PARAMETER INSTANCE = DIP_Switches_4Bit
 PARAMETER C_ALL_INPUTS = 1
 PARAMETER C_GPIO_WIDTH = 4
 PARAMETER C_INTERRUPT_PRESENT = 0
 PARAMETER C_IS_DUAL = 0
 PARAMETER HW_VER = 2.00.a
 PARAMETER C_BASEADDR = 0x81440000
 PARAMETER C_HIGHADDR = 0x8144ffff
 BUS_INTERFACE SPLB = mb_plb
 PORT GPIO_IO_I = fpga_0_DIP_Switches_4Bit_GPIO_IO_I_pin
END

BEGIN clock_generator
 PARAMETER INSTANCE = clock_generator_0
 PARAMETER HW_VER = 3.02.a
 PARAMETER C_EXT_RESET_HIGH = 1
 PARAMETER C_PLL0_REF_JITTER = 0.005
 PARAMETER C_CLKIN_FREQ = 200000000
 PARAMETER C_CLKOUT0_FREQ = 666666667
 PARAMETER C_CLKOUT0_BUF = FALSE
 PARAMETER C_CLKOUT0_PHASE = 0
 PARAMETER C_CLKOUT0_GROUP = PLL0
 PARAMETER C_CLKOUT1_FREQ = 666666667
 PARAMETER C_CLKOUT1_BUF = FALSE
 PARAMETER C_CLKOUT1_PHASE = 180
 PARAMETER C_CLKOUT1_GROUP = PLL0
 PARAMETER C_CLKOUT2_FREQ = 95238095
 PARAMETER C_CLKOUT2_BUF = TRUE
 PARAMETER C_CLKOUT2_PHASE = 0
 PARAMETER C_CLKOUT2_GROUP = PLL0
 PORT CLKOUT0 = pll_module_0_CLKOUT0
 PORT CLKOUT1 = pll_module_0_CLKOUT1
 PORT CLKOUT2 = sys_clk_s
 PORT CLKIN = dcm_clk_s
 PORT LOCKED = clock_generator_0_locked
 PORT RST = sys_rst_s
END

BEGIN mpmc
 PARAMETER INSTANCE = DDR2_SDRAM
 PARAMETER HW_VER = 5.04.a
 PARAMETER C_NUM_PORTS = 2
 PARAMETER C_MEM_PARTNO = EDE1116AXXX-8E
 PARAMETER C_MEM_ODT_TYPE = 3
 PARAMETER C_DDR2_DQSN_ENABLE = 1
 PARAMETER C_MEM_CALIBRATION_SOFT_IP = TRUE
 PARAMETER C_MEM_SKIP_IN_TERM_CAL = 0
 PARAMETER C_MEM_SKIP_DYNAMIC_CAL = 0
 PARAMETER C_PORT_CONFIG = 1
 PARAMETER C_MEM_DATA_WIDTH = 16
 PARAMETER C_MEM_TYPE = DDR2
# PIM0 (XCL)
 PARAMETER C_PIM0_BASETYPE = 1
 PARAMETER C_XCL0_B_IN_USE = 1
# PIM1 (PLBV46 PIM)
 PARAMETER C_PIM1_BASETYPE = 2
 PARAMETER C_SPLB1_NATIVE_DWIDTH = 32
 PARAMETER C_PI1_RD_FIFO_APP_PIPELINE = 0
 PARAMETER C_MCB_LOC = MEMC3
 PARAMETER C_MPMC_BASEADDR = 0xc8000000
 PARAMETER C_MPMC_HIGHADDR = 0xcfffffff
 BUS_INTERFACE XCL0 = microblaze_0_DXCL
 BUS_INTERFACE XCL0_B = microblaze_0_IXCL
 BUS_INTERFACE SPLB1 = mb_plb
 PORT MPMC_Rst = mpmc_rst
 PORT MPMC_PLL_Lock = clock_generator_0_locked
 PORT MPMC_Clk0 = sys_clk_s
 PORT MPMC_Clk_Mem_2x = pll_module_0_CLKOUT0
 PORT MPMC_Clk_Mem_2x_180 = pll_module_0_CLKOUT1
# DDR2 Pins
 PORT mcbx_dram_addr = MPMC_0_mcbx_dram_addr
 PORT mcbx_dram_ba = MPMC_0_mcbx_dram_ba
 PORT mcbx_dram_ras_n = MPMC_0_mcbx_dram_ras_n
 PORT mcbx_dram_cas_n = MPMC_0_mcbx_dram_cas_n
 PORT mcbx_dram_we_n = MPMC_0_mcbx_dram_we_n
 PORT mcbx_dram_cke = MPMC_0_mcbx_dram_cke
 PORT mcbx_dram_clk = MPMC_0_mcbx_dram_clk
 PORT mcbx_dram_clk_n = MPMC_0_mcbx_dram_clk_n
 PORT mcbx_dram_dq = MPMC_0_mcbx_dram_dq
 PORT mcbx_dram_dqs = MPMC_0_mcbx_dram_dqs
 PORT mcbx_dram_udqs = MPMC_0_mcbx_dram_udqs
 PORT mcbx_dram_odt = MPMC_0_mcbx_dram_odt
 PORT mcbx_dram_ldm = MPMC_0_mcbx_dram_ldm
 PORT mcbx_dram_udm = MPMC_0_mcbx_dram_udm
 PORT mcbx_dram_udqs_n = MPMC_0_mcbx_dram_udqs_n
 PORT mcbx_dram_dqs_n = MPMC_0_mcbx_dram_dqs_n
 PORT rzq = MPMC_0_mcbx_dram_rzq
 PORT zio = MPMC_0_mcbx_dram_zio
END

BEGIN proc_sys_reset
 PARAMETER INSTANCE = proc_sys_reset_0
 PARAMETER HW_VER = 2.00.a
 PARAMETER C_EXT_RESET_HIGH = 1
 PARAMETER C_NUM_BUS_RST = 2
 PORT Slowest_sync_clk = sys_clk_s
 PORT Dcm_locked = clock_generator_0_locked
 PORT Ext_Reset_In = sys_rst_s
 PORT MB_Reset = mb_reset
 PORT Bus_Struct_Reset = sys_bus_reset & mpmc_rst
 PORT Peripheral_Reset = sys_periph_reset
 PORT MB_Debug_Sys_Rst = Debug_SYS_Rst
END

BEGIN xps_intc
 PARAMETER INSTANCE = Interrupt_Cntlr
 PARAMETER HW_VER = 2.00.a
 PARAMETER C_BASEADDR = 0x81800000
 PARAMETER C_HIGHADDR = 0x8180ffff
 BUS_INTERFACE SPLB = mb_plb
 PORT Irq = Interrupt
 PORT Intr = RS232_Uart_1_IP2INTC_Irpt&Timer_Counter_Interrupt&SPI_FLASH_IP2INTC_Irpt&Ethernet_MAC_IP2INTC_Irpt&IIC_EEPROM_IIC2INTC_Irpt
END

BEGIN xps_timer
 PARAMETER INSTANCE = Timer_Counter
 PARAMETER HW_VER = 1.01.b
 PARAMETER C_COUNT_WIDTH = 32
 PARAMETER C_ONE_TIMER_ONLY = 1
 PARAMETER C_BASEADDR = 0x83c00000
 PARAMETER C_HIGHADDR = 0x83c0ffff
 BUS_INTERFACE SPLB = mb_plb
 PORT Interrupt = Timer_Counter_Interrupt
END

BEGIN xps_gpio
 PARAMETER INSTANCE = Push_Buttons_4Bit
 PARAMETER HW_VER = 2.00.a
 PARAMETER C_GPIO_WIDTH = 5
 PARAMETER C_IS_DUAL = 0
 PARAMETER C_ALL_INPUTS = 1
 PARAMETER C_BASEADDR = 0x81400000
 PARAMETER C_HIGHADDR = 0x8140ffff
 BUS_INTERFACE SPLB = mb_plb
 PORT GPIO_IO = fpga_0_Push_Buttons_4Bit_GPIO_IO
END

BEGIN xps_iic
 PARAMETER INSTANCE = IIC_EEPROM
 PARAMETER HW_VER = 2.02.a
 PARAMETER C_CLK_FREQ = 95238095
 PARAMETER C_IIC_FREQ = 100000
 PARAMETER C_TEN_BIT_ADR = 0
 PARAMETER C_BASEADDR = 0x81600000
 PARAMETER C_HIGHADDR = 0x8160ffff
 BUS_INTERFACE SPLB = mb_plb
 PORT Scl = fpga_0_IIC_EEPROM_Scl
 PORT Sda = fpga_0_IIC_EEPROM_Sda
 PORT IIC2INTC_Irpt = IIC_EEPROM_IIC2INTC_Irpt
END

BEGIN xps_mch_emc
 PARAMETER INSTANCE = FLASH
 PARAMETER HW_VER = 3.01.a
 PARAMETER C_NUM_CHANNELS = 0
 PARAMETER C_NUM_BANKS_MEM = 1
 PARAMETER C_MAX_MEM_WIDTH = 8
 PARAMETER C_MEM0_WIDTH = 8
 PARAMETER C_INCLUDE_DATAWIDTH_MATCHING_0 = 1
 PARAMETER C_SYNCH_MEM_0 = 0
 PARAMETER C_TCEDV_PS_MEM_0 = 70000
 PARAMETER C_TAVDV_PS_MEM_0 = 70000
 PARAMETER C_TWC_PS_MEM_0 = 70000
 PARAMETER C_TWP_PS_MEM_0 = 45000
 PARAMETER C_THZOE_PS_MEM_0 = 25000
 PARAMETER C_THZCE_PS_MEM_0 = 25000
 PARAMETER C_TLZWE_PS_MEM_0 = 5000
 PARAMETER C_MEM0_BASEADDR = 0xc5000000
 PARAMETER C_MEM0_HIGHADDR = 0xc5ffffff
 BUS_INTERFACE SPLB = mb_plb
 PORT Mem_A = fpga_0_FLASH_Mem_A_split
 PORT Mem_WEN = fpga_0_FLASH_Mem_WEN
 PORT Mem_DQ_I = fpga_0_FLASH_Mem_DQ_I
 PORT Mem_DQ_O = fpga_0_FLASH_Mem_DQ_O
 PORT Mem_DQ_T = fpga_0_FLASH_Mem_DQ_T
 PORT Mem_OEN = fpga_0_FLASH_Mem_OEN
 PORT Mem_CEN = fpga_0_FLASH_Mem_CEN
 PORT Mem_RPN = fpga_0_FLASH_Mem_RPN
 PORT RdClk = sys_clk_s
END

BEGIN xps_spi
 PARAMETER INSTANCE = SPI_FLASH
 PARAMETER HW_VER = 2.01.b
 PARAMETER C_BASEADDR = 0x83400000
 PARAMETER C_HIGHADDR = 0x8340ffff
 BUS_INTERFACE SPLB = mb_plb
 PORT IP2INTC_Irpt = SPI_FLASH_IP2INTC_Irpt
 PORT SPISEL = net_vcc
 PORT MISO_I = fpga_0_SPI_FLASH_MISO_I
 PORT MISO_O = fpga_0_SPI_FLASH_MISO_O
 PORT MISO_T = fpga_0_SPI_FLASH_MISO_T
 PORT MOSI = fpga_0_SPI_FLASH_MOSI
 PORT SCK = fpga_0_SPI_FLASH_SCK
 PORT SS = fpga_0_SPI_FLASH_SS
END

BEGIN util_io_mux
 PARAMETER INSTANCE = util_io_mux_0
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_SIZE = 8
 PORT S = fpga_0_FLASH_Mem_CEN
 PORT I0 = fpga_0_FLASH_Mem_DQ_I
 PORT O0 = fpga_0_FLASH_Mem_DQ_O
 PORT T0 = fpga_0_FLASH_Mem_DQ_T
 PORT I1 = 0b0000000&fpga_0_SPI_FLASH_MISO_I
 PORT O1 = 0b1111111&fpga_0_SPI_FLASH_MISO_O
 PORT T1 = 0b1111111&fpga_0_SPI_FLASH_MISO_T
 PORT IO = fpga_0_FLASH_Mem_DQ_Shared
END

BEGIN util_bus_split
 PARAMETER INSTANCE = FLASH_util_bus_split_0
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_SIZE_IN = 32
 PARAMETER C_LEFT_POS = 0
 PARAMETER C_SPLIT = 8
 PORT Sig = fpga_0_FLASH_Mem_A_split
 PORT Out2 = fpga_0_FLASH_Mem_A
END

BEGIN xps_ethernetlite
 PARAMETER INSTANCE = Ethernet_MAC
 PARAMETER HW_VER = 3.01.a
 PARAMETER C_INCLUDE_INTERNAL_LOOPBACK = 1
 PARAMETER C_BASEADDR = 0x81100000
 PARAMETER C_HIGHADDR = 0x8110ffff
 BUS_INTERFACE SPLB = mb_plb
 PORT PHY_tx_clk = fpga_0_Ethernet_MAC_PHY_tx_clk_pin
 PORT PHY_rx_clk = fpga_0_Ethernet_MAC_PHY_rx_clk_pin
 PORT PHY_crs = fpga_0_Ethernet_MAC_PHY_crs_pin
 PORT PHY_dv = fpga_0_Ethernet_MAC_PHY_dv_pin
 PORT PHY_rx_data = fpga_0_Ethernet_MAC_PHY_rx_data_pin
 PORT PHY_col = fpga_0_Ethernet_MAC_PHY_col_pin
 PORT PHY_rx_er = fpga_0_Ethernet_MAC_PHY_rx_er_pin
 PORT PHY_rst_n = fpga_0_Ethernet_MAC_PHY_rst_n_pin
 PORT PHY_tx_en = fpga_0_Ethernet_MAC_PHY_tx_en_pin
 PORT PHY_tx_data = fpga_0_Ethernet_MAC_PHY_tx_data_pin
 PORT PHY_MDC = fpga_0_Ethernet_MAC_PHY_MDC_pin
 PORT PHY_MDIO = fpga_0_Ethernet_MAC_PHY_MDIO_pin
 PORT IP2INTC_Irpt = Ethernet_MAC_IP2INTC_Irpt
END

BEGIN demoip
 PARAMETER INSTANCE = demoip_0
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_BASEADDR = 0xc1000000
 PARAMETER C_HIGHADDR = 0xc100ffff
 BUS_INTERFACE SPLB = mb_plb
END

0 Kudos
7,468 Views
Registered: ‎06-29-2009

Re: Custom IP has no conected BUS2IP_DATA(0:31) for the user_logic

Jump to solution

Hi,

 

Thanx for the demo.  I analyze it and changed a litle bit my code.   But I still have the Bus2IPdata not connected. 

 

I also did read in the warnings:

 -  Input <Bus2IP_BE<0:3>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

It give a lot of those warnings, and I wass starting to wonder if I should focus on the fact that the RTL had an unconnected signal/vector.  Will XPS recompile this and maybe not produce this fenomena?

 

Then I commented a port of the code in the user logic (in the RegWrite Proces) like following:

case slv_reg_write_sel is
          when "1000" =>
            for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
             -- if ( Bus2IP_BE(byte_index) = '1' ) then
                slv_reg0(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
             -- end if;
            end loop;

       . . . 

And then it did connected the BUS2IP_DATA in the RTL schematic ...    off course I guess it's not the way to work (but I try to understand how it works and what happens)


 

 

So, now I have this code ...  I will try some extra things tomorrow.  But I am quit confused on why it fails.

 

 


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;


entity user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------

-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_SLV_DWIDTH : integer := 32;
C_NUM_REG : integer := 4
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
-- ADD USER PORTS ABOVE THIS LINE ------------------

-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Data : in std_logic_vector(0 to C_SLV_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to C_SLV_DWIDTH/8-1);
Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_REG-1);
Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_REG-1);
IP2Bus_Data : out std_logic_vector(0 to C_SLV_DWIDTH-1);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);

attribute SIGIS : string;
attribute SIGIS of Bus2IP_Clk : signal is "CLK";
attribute SIGIS of Bus2IP_Reset : signal is "RST";

end entity user_logic;

------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------

architecture IMP of user_logic is

--USER signal declarations added here, as needed for user logic


signal icapOut : std_logic_vector(0 to 15);
signal icapIn : std_logic_vector(15 downto 0);
signal icapWrite : std_logic;
signal icapClk : std_logic;
signal icapCE : std_logic;
signal icapBusy : std_logic;





component icap_spartan6
port (
BUSY : out std_logic; -- 1-bit Busy output
O : out std_logic_vector(15 downto 0); -- 16-bit Configuartion data output bus
CE : in std_logic; -- 1-bit Active low clock enable input
CLK : in std_logic; -- 1-bit Clock input
I : in std_logic_vector(15 downto 0); -- 16-bit Configuration data input bus
WRITE : in std_logic);
end component;

------------------------------------------
-- Signals for user logic slave model s/w accessible register example
------------------------------------------

signal slv_reg0 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg1 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg2 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg3 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg_write_sel : std_logic_vector(0 to 3);
signal slv_reg_read_sel : std_logic_vector(0 to 3);
signal slv_ip2bus_data : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_read_ack : std_logic;
signal slv_write_ack : std_logic;


begin


---instance of ICAP6
---------------------------

ICAP_SPARTAN6_inst : icap_spartan6
port map (
BUSY => icapBusy, -- 1-bit Busy output

O(15) => icapOut(15), -- 16-bit Configuartion data output bus
O(14) => icapOut(14), -- 16-bit Configuartion data output bus
O(13) => icapOut(13), -- 16-bit Configuartion data output bus
O(12) => icapOut(12), -- 16-bit Configuartion data output bus
O(11) => icapOut(11), -- 16-bit Configuartion data output bus
O(10) => icapOut(10), -- 16-bit Configuartion data output bus
O(9) => icapOut(9), -- 16-bit Configuartion data output bus
O(8) => icapOut(8), -- 16-bit Configuartion data output bus
O(7) => icapOut(7), -- 16-bit Configuartion data output bus
O(6) => icapOut(6), -- 16-bit Configuartion data output bus
O(5) => icapOut(5), -- 16-bit Configuartion data output bus
O(4) => icapOut(4), -- 16-bit Configuartion data output bus
O(3) => icapOut(3), -- 16-bit Configuartion data output bus
O(2) => icapOut(2), -- 16-bit Configuartion data output bus
O(1) => icapOut(1), -- 16-bit Configuartion data output bus
O(0) => icapOut(0), -- 16-bit Configuartion data output bus

CE => slv_reg0(2), -- 1-bit Active low clock enable input
CLK => slv_reg0(1), -- 1-bit Clock input

I(15) => slv_reg2(8), -- 16-bit Configuration data input bus
I(14) => slv_reg2(9), -- 16-bit Configuration data input bus
I(13) => slv_reg2(10), -- 16-bit Configuration data input bus
I(12) => slv_reg2(11), -- 16-bit Configuration data input bus
I(11) => slv_reg2(12), -- 16-bit Configuration data input bus
I(10) => slv_reg2(13), -- 16-bit Configuration data input bus
I(9) => slv_reg2(14), -- 16-bit Configuration data input bus
I(8) => slv_reg2(15), -- 16-bit Configuration data input bus
I(7) => slv_reg2(0), -- 16-bit Configuration data input bus
I(6) => slv_reg2(1), -- 16-bit Configuration data input bus
I(5) => slv_reg2(2), -- 16-bit Configuration data input bus
I(4) => slv_reg2(3), -- 16-bit Configuration data input bus
I(3) => slv_reg2(4), -- 16-bit Configuration data input bus
I(2) => slv_reg2(5), -- 16-bit Configuration data input bus
I(1) => slv_reg2(6), -- 16-bit Configuration data input bus
I(0) => slv_reg2(7), -- 16-bit Configuration data input bus

WRITE => slv_reg0(0) -- 1-bit Active low write input
);



--USER logic implementation added here

------------------------------------------
-- Example code to read/write user logic slave model s/w accessible registers
--
-- Note:
-- The example code presented here is to show you one way of reading/writing
-- software accessible registers implemented in the user logic slave model.
-- Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond
-- to one software accessible register by the top level template. For example,
-- if you have four 32 bit software accessible registers in the user logic,
-- you are basically operating on the following memory mapped registers:
--
-- Bus2IP_WrCE/Bus2IP_RdCE Memory Mapped Register
-- "1000" C_BASEADDR + 0x0
-- "0100" C_BASEADDR + 0x4
-- "0010" C_BASEADDR + 0x8
-- "0001" C_BASEADDR + 0xC
--
------------------------------------------
slv_reg_write_sel <= Bus2IP_WrCE(0 to 3);
slv_reg_read_sel <= Bus2IP_RdCE(0 to 3);
slv_write_ack <= Bus2IP_WrCE(0) or Bus2IP_WrCE(1) or Bus2IP_WrCE(2) or Bus2IP_WrCE(3);
slv_read_ack <= Bus2IP_RdCE(0) or Bus2IP_RdCE(1) or Bus2IP_RdCE(2) or Bus2IP_RdCE(3);

-- implement slave model software accessible register(s)
SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is
begin

if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Reset = '1' then
slv_reg0 <= (others => '0');
slv_reg1 <= (others => '0');
slv_reg2 <= (others => '0');
slv_reg3 <= (others => '0');
else
case slv_reg_write_sel is
when "1000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
-- if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg0(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
-- end if;
end loop;
when "0100" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
-- if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg1(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
-- end if;
end loop;
when "0010" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
-- if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg2(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
-- end if;
end loop;
when "0001" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
-- if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg3(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
-- end if;
end loop;
when others => null;
end case;
end if;
end if;

end process SLAVE_REG_WRITE_PROC;

-- implement slave model software accessible register(s) read mux
SLAVE_REG_READ_PROC : process( slv_reg_read_sel, slv_reg0, slv_reg1, slv_reg2, slv_reg3 ) is
begin

case slv_reg_read_sel is

when "1000" =>
slv_ip2bus_data <= slv_reg0;

when "0100" =>
slv_ip2bus_data(0) <= icapBusy;
slv_ip2bus_data(1 to 31) <= (others => '0');

when "0010" =>
slv_ip2bus_data <= slv_reg2;

when "0001" =>
slv_ip2bus_data(0 to 15) <= icapOut(0 to 15);

slv_ip2bus_data(16 to 31) <= (others => '0');

when others => slv_ip2bus_data <= (others => '0');

end case;

end process SLAVE_REG_READ_PROC;

------------------------------------------
-- Example code to drive IP to Bus signals
------------------------------------------
IP2Bus_Data <= slv_ip2bus_data when slv_read_ack = '1' else
(others => '0');

IP2Bus_WrAck <= slv_write_ack;
IP2Bus_RdAck <= slv_read_ack;
IP2Bus_Error <= '0';

end IMP;

 

 

 

Message Edited by serge.kubera@ehb.be on 03-03-2010 04:08 PM
0 Kudos
9,484 Views
Registered: ‎06-29-2009

Re: Custom IP has no conected BUS2IP_DATA(0:31) for the user_logic

Jump to solution

After some test, the next conclusion has been made:

 

  -  The connection is actualy made ,  but it is just not drawed in the RTL schematic.

 

Serge

 

Message Edited by serge.kubera@ehb.be on 03-03-2010 04:11 PM
0 Kudos