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Contributor
Contributor
552 Views
Registered: ‎06-10-2019

DDR Less ZC702

Hi All,

I am working to check working of DDR less booting on ZC702 evaluation kit, I am following the tech+tip @ https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842377/Zynq-7000+AP+SoC+Boot+-+Booting+and+Running+Without+External+Memory+Tech+Tip

I have downloaded Zynq7000AP_SoC_BootingWithoutExternalMemory_2017_3.zip & imported the project to XSDK 2019.1 as below

Capture1.PNG

All binaries generated upon build, inspite of the below error

c:/xilinx/sdk/2019.1/gnu/aarch32/nt/gcc-arm-none-eabi/bin/../lib/gcc/arm-none-eabi/8.2.0/../../../../arm-none-eabi/bin/ld.exe: FSBL_XIP.elf: section `.data' can't be allocated in segment 0

 

I have tried to create a boot-image following Reference_Design_Files\Bootgen\bootimage.bif sdf following is the file created


//arch = zynq; split = false; format = BIN
the_ROM_image:
{
[bootloader, xip_mode, offset = 0x2000]C:\Users\212761946\Documents\MiCom\ZC702\DDRLess\ws_software_project\FSBL_XIP\Debug\FSBL_XIP.elf
[offset = 0x200000]C:\Users\Vamshi\ZC702\DDRLess\ws_software_project\design_noddr_wrapper_hw_platform_0\design_noddr_wrapper.bit
[offset = 0x700000]C:\Users\Vamshi\ZC702\DDRLess\ws_software_project\Application\Debug\Application.elf
}


After creating BOOT.bin, when I tried to flash the device from Xilinx -> Program Flash, I am seeing the below error


Note: Device is palced in JTAG mode

image2019-7-19_12-6-21.png


cmd /C program_flash -f \
C:\Users\Vamshi\ZC702\DDRLess\ws_software_project\BOOT.bin -offset 0 \
-flash_type qspi-x4-single -fsbl \
C:\Users\Vamshi\ZC702\DDRLess\ws_software_project\FSBL_XIP\Debug\FSBL_XIP.elf \
-verify -cable type xilinx_tcf url TCP:127.0.0.1:3121

****** Xilinx Program Flash
****** Program Flash v2019.1 (64-bit)
**** SW Build 2552052 on Fri May 24 14:49:42 MDT 2019
** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.


Connected to hw_server @ TCP:127.0.0.1:3121
Available targets and devices:
Target 0 : jsn-JTAG-SMT1-210203327050A
Target 1 : jsn-JTAG-SMT1-210203A03623A
Device 0: jsn-JTAG-SMT1-210203A03623A-4ba00477-0

Retrieving Flash info...

Initialization done, programming the memory
===== mrd->addr=0xF800025C, data=0x00000000 =====
BOOT_MODE REG = 0x00000000
Downloading FSBL...
===== mrd->addr=0xF8000110, data=0x00177EA0 =====
READ: ARM_PLL_CFG (0xF8000110) = 0x00177EA0
===== mrd->addr=0xF8000100, data=0x0001A008 =====
READ: ARM_PLL_CTRL (0xF8000100) = 0x0001A008
===== mrd->addr=0xF8000120, data=0x1F000400 =====
READ: ARM_CLK_CTRL (0xF8000120) = 0x1F000400
===== mrd->addr=0xF8000118, data=0x00177EA0 =====
READ: IO_PLL_CFG (0xF8000118) = 0x00177EA0
===== mrd->addr=0xF8000108, data=0x0001A008 =====
READ: IO_PLL_CTRL (0xF8000108) = 0x0001A008
Problem in Initializing Hardware
Flash programming initialization failed.

ERROR: Flash Operation Failed


Where as I am able to program a HelloWorld project created from XSDK, this is clear that there is no issue with hardware & QSPI.

 

I also tried to flash with the pre-built binarires provided @ Zynq7000AP_SoC_BootingWithoutExternalMemory_2017_3\Reference_Design_Files\generated_files

Capture.PNG

still the SAME ERROR !

 

Please give your inputs to resolve this!

 

Thanks & Regards,

Vamshi G.

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8 Replies
Contributor
Contributor
490 Views
Registered: ‎06-10-2019

Re: DDR Less ZC702

awaiting your respone! Thansk in advance.

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Xilinx Employee
Xilinx Employee
474 Views
Registered: ‎06-21-2018

Re: DDR Less ZC702

Hi vamshi,

I believe there might be an issue with the FSBL you're using.

Take a look at this AR: https://www.xilinx.com/support/answers/70148.html

And this Forum thread:
https://forums.xilinx.com/t5/ACAP-and-SoC-Boot-and/Can-t-flash-QSPI/td-p/813536

Thanks,
Andres

 

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Contributor
Contributor
408 Views
Registered: ‎06-10-2019

Re: DDR Less ZC702

Hi @andresb ,

 

Thanks for your pointers. As per the links I have used a full-fledge FSBL while flashing QSPI, I am able to program memory, however I am unable to see prints over UART, while boot from QSPI. 

I went through the post https://forums.xilinx.com/t5/ACAP-and-SoC-Boot-and/Can-t-flash-QSPI/td-p/813536 which tightly describes w.r.t 2017.1 version of SDK, I see the desribed chages are present in the code Zynq7000AP_SoC_BootingWithoutExternalMemory_2017_3.zip

Please point me to the latest code that you have tested working.

Thanks & Regards,

Vamshi G.

 

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Xilinx Employee
Xilinx Employee
384 Views
Registered: ‎06-21-2018

Re: DDR Less ZC702

Hi vamshi,

If you download the bitfile instead of booting from the QSPI, are you able to see prints over UART? 

I haven't tested any of the code, maybe some other user has.

Thanks,
Andres

 

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Contributor
Contributor
371 Views
Registered: ‎06-10-2019

Re: DDR Less ZC702

Hi @andresb ,

When I flashed BOOT.bin, during lash I have see the print "Devcfg driver initialized" on serial console @ 115200 baud.

 

After program successful, I have changed bootmode to QSPI & did power on, I see there are no prints on serial console.

 

Please help me to verify this feature at your end.

 

Thanks & Regards,

Vamshi G.

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Contributor
Contributor
318 Views
Registered: ‎06-10-2019

Re: DDR Less ZC702

Dear Team,

Please give your inputs on this item.

 

Thanks & Regards,

Vamshi G.

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Xilinx Employee
Xilinx Employee
293 Views
Registered: ‎06-21-2018

Re: DDR Less ZC702

Hi vamshi,

I'll ask the Moderator to move this thread to the Embedded board. They might be able to help you there.

Thanks,
Andres

 

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Contributor
Contributor
268 Views
Registered: ‎06-10-2019

Re: DDR Less ZC702

@andresb 

 

Thank you, please do needful.

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