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Visitor kuganv
Visitor
6,353 Views
Registered: ‎06-10-2008

Debugging multiple Microblaze with MDM

I am creating a design with two microblaze instances as bellow. However, when i connect to it in mdm with  "connect mb mdm" i can only see one processor. Am i missing or doing anything wrong ?

 


 PARAMETER VERSION = 2.2.0


BEGIN OS
 PARAMETER OS_NAME = standalone
 PARAMETER OS_VER = 1.00.a
 PARAMETER PROC_INSTANCE = microblaze_0
 PARAMETER STDIN = RS232_Uart
 PARAMETER STDOUT = RS232_Uart
END

BEGIN OS
 PARAMETER OS_NAME = standalone
 PARAMETER OS_VER = 1.00.a
 PARAMETER PROC_INSTANCE = microblaze_1
END


BEGIN PROCESSOR
 PARAMETER DRIVER_NAME = cpu
 PARAMETER DRIVER_VER = 1.01.a
 PARAMETER HW_INSTANCE = microblaze_0
 PARAMETER COMPILER = mb-gcc
 PARAMETER ARCHIVER = mb-ar
 PARAMETER XMDSTUB_PERIPHERAL = debug_module
END

BEGIN PROCESSOR
 PARAMETER DRIVER_NAME = cpu
 PARAMETER DRIVER_VER = 1.01.a
 PARAMETER HW_INSTANCE = microblaze_1
 PARAMETER COMPILER = mb-gcc
 PARAMETER ARCHIVER = mb-ar
END


BEGIN DRIVER
 PARAMETER DRIVER_NAME = opbarb
 PARAMETER DRIVER_VER = 1.02.a
 PARAMETER HW_INSTANCE = mb_opb
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = uartlite
 PARAMETER DRIVER_VER = 1.01.a
 PARAMETER HW_INSTANCE = debug_module
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = bram
 PARAMETER DRIVER_VER = 1.00.a
 PARAMETER HW_INSTANCE = dlmb_cntlr
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = bram
 PARAMETER DRIVER_VER = 1.00.a
 PARAMETER HW_INSTANCE = ilmb_cntlr
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = uartlite
 PARAMETER DRIVER_VER = 1.01.a
 PARAMETER HW_INSTANCE = RS232_Uart
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = sdram
 PARAMETER DRIVER_VER = 1.00.a
 PARAMETER HW_INSTANCE = DDR_SDRAM_64Mx32
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = emc
 PARAMETER DRIVER_VER = 2.00.a
 PARAMETER HW_INSTANCE = SRAM_256Kx32
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = bram
 PARAMETER DRIVER_VER = 1.00.a
 PARAMETER HW_INSTANCE = lmb_bram_if_cntlr_0
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = bram
 PARAMETER DRIVER_VER = 1.00.a
 PARAMETER HW_INSTANCE = lmb_bram_if_cntlr_1
END

Output

======XMD% connect mb mdm
Reusing 78020001 key.
Reusing FC020001 key.
Connecting to cable (Parallel Port - parport0).
 libusb-driver.so version: 2008-01-20 20:17:11.
 parport0: baseAddress=0x0, ecpAddress=0x400
 LPT base address = 0000h.
 ECP base address = 0400h.
Can't open /dev/parport0: Permission denied
LPT port is already in use. rc = FFFFFFFFh
Cable connection failed.
Reusing 78020001 key.
Reusing FC020001 key.
Connecting to cable (Parallel Port - parport0).
 libusb-driver.so version: 2008-01-20 20:17:11.
 LPT base address = 0000h.
 ECP base address = 0400h.
Can't open /dev/parport0: Permission denied
LPT port is already in use. rc = FFFFFFFFh
Cable connection failed.
Reusing 79020001 key.
Reusing FD020001 key.
Connecting to cable (Parallel Port - parport1).
 libusb-driver.so version: 2008-01-20 20:17:11.
Cable connection failed.
Reusing 79020001 key.
Reusing FD020001 key.
Connecting to cable (Parallel Port - parport1).
 libusb-driver.so version: 2008-01-20 20:17:11.
Cable connection failed.
Connecting to cable (Usb Port - USB22).
Checking cable driver.
File version of /opt/ISE8.2i/bin/lin/xusbdfwu.hex = 1021(dec), 03FD.
File version of /etc/hotplug/usb/xusbdfwu.fw/xusbdfwu.hex = 1030(dec), 0406.
Calling setinterface num=0, alternate=0.
DeviceAttach: received and accepted attach for:
  vendor id 0x3fd, product id 0x8, device handle 0x89ac258
 Cable PID = 0008.
 Max current requested during enumeration is 280 mA.
 Cable Type = 3, Revision = 0.
 Setting cable speed to 6 MHz.
Cable connection established.
Firmware version = 1030.
CPLD file version = 0012h.
CPLD version = 0012h.

JTAG chain configuration
--------------------------------------------------
Device   ID Code        IR Length    Part Name
 1       0a001093           8        System_ACE
 2       05059093          16        XCF32P
 3       01e58093          10        XC4VFX12
 4       09608093           8        xc95144xl
Assuming, Device No: 3 contains the MicroBlaze system
Connected to the JTAG MicroProcessor Debug Module (MDM)
No of processors = 1

MicroBlaze Processor 1 Configuration :
-------------------------------------
Version............................5.00.c
No of PC Breakpoints...............2
No of Read Addr/Data Watchpoints...0
No of Write Addr/Data Watchpoints..0
Instruction Cache Support..........off
Data Cache Support.................off
Exceptions  Support................off
FPU  Support.......................off
FSL DCache Support.................on
FSL ICache Support.................on
Hard Divider Support...............off
Hard Multiplier Support............on
Barrel Shifter Support.............off
MSR clr/set Instruction Support....on
Compare Instruction Support........on
PVR Supported......................off
JTAG MDM Connected to MicroBlaze 1
Connected to "mb" target. id = 0
Starting GDB server for "mb" target (id = 0) at TCP port no 1234
XMD%

 

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4 Replies
Visitor kuganv
Visitor
6,350 Views
Registered: ‎06-10-2008

Re: Debugging multiple Microblaze with MDM

Sorry. Here is the mhs file

 

# ##############################################################################
# Created by Base System Builder Wizard for Xilinx EDK 8.2.02 Build EDK_Im_Sp2.4
# Fri Jun 27 09:30:09 2008
# Target Board:  Xilinx Virtex 4 ML403 Evaluation Platform Rev 1
# Family:     virtex4
# Device:     xc4vfx12
# Package:     ff668
# Speed Grade:     -10
# Processor: Microblaze
# System clock frequency: 100.000000 MHz
# Debug interface: On-Chip HW Debug Module
# On Chip Memory :   8 KB
# Total Off Chip Memory :  65 MB
# - DDR_SDRAM_32Mx32 =  64 MB
# - SRAM_256Kx32 =   1 MB
# ##############################################################################


 PARAMETER VERSION = 2.1.0


 PORT fpga_0_RS232_Uart_RX_pin = fpga_0_RS232_Uart_RX, DIR = I
 PORT fpga_0_RS232_Uart_TX_pin = fpga_0_RS232_Uart_TX, DIR = O
 PORT fpga_0_DDR_SDRAM_64Mx32_DDR_Clk_pin = fpga_0_DDR_SDRAM_64Mx32_DDR_Clk, DIR = O
 PORT fpga_0_DDR_SDRAM_64Mx32_DDR_Clkn_pin = fpga_0_DDR_SDRAM_64Mx32_DDR_Clkn, DIR = O
 PORT fpga_0_DDR_SDRAM_64Mx32_DDR_Addr_pin = fpga_0_DDR_SDRAM_64Mx32_DDR_Addr, DIR = O, VEC = [0:12]
 PORT fpga_0_DDR_SDRAM_64Mx32_DDR_BankAddr_pin = fpga_0_DDR_SDRAM_64Mx32_DDR_BankAddr, DIR = O, VEC = [0:1]
 PORT fpga_0_DDR_SDRAM_64Mx32_DDR_CASn_pin = fpga_0_DDR_SDRAM_64Mx32_DDR_CASn, DIR = O
 PORT fpga_0_DDR_SDRAM_64Mx32_DDR_CKE_pin = fpga_0_DDR_SDRAM_64Mx32_DDR_CKE, DIR = O
 PORT fpga_0_DDR_SDRAM_64Mx32_DDR_CSn_pin = fpga_0_DDR_SDRAM_64Mx32_DDR_CSn, DIR = O
 PORT fpga_0_DDR_SDRAM_64Mx32_DDR_RASn_pin = fpga_0_DDR_SDRAM_64Mx32_DDR_RASn, DIR = O
 PORT fpga_0_DDR_SDRAM_64Mx32_DDR_WEn_pin = fpga_0_DDR_SDRAM_64Mx32_DDR_WEn, DIR = O
 PORT fpga_0_DDR_SDRAM_64Mx32_DDR_DM_pin = fpga_0_DDR_SDRAM_64Mx32_DDR_DM, DIR = O, VEC = [0:3]
 PORT fpga_0_DDR_SDRAM_64Mx32_DDR_DQS_pin = fpga_0_DDR_SDRAM_64Mx32_DDR_DQS, DIR = IO, VEC = [0:3]
 PORT fpga_0_DDR_SDRAM_64Mx32_DDR_DQ_pin = fpga_0_DDR_SDRAM_64Mx32_DDR_DQ, DIR = IO, VEC = [0:31]
 PORT fpga_0_SRAM_256Kx32_Mem_A_pin = fpga_0_SRAM_256Kx32_Mem_A, DIR = O, VEC = [9:29]
 PORT fpga_0_SRAM_256Kx32_Mem_BEN_pin = fpga_0_SRAM_256Kx32_Mem_BEN, DIR = O, VEC = [0:3]
 PORT fpga_0_SRAM_256Kx32_Mem_WEN_pin = fpga_0_SRAM_256Kx32_Mem_WEN, DIR = O
 PORT fpga_0_SRAM_256Kx32_Mem_DQ_pin = fpga_0_SRAM_256Kx32_Mem_DQ, DIR = IO, VEC = [0:31]
 PORT fpga_0_SRAM_256Kx32_Mem_OEN_pin = fpga_0_SRAM_256Kx32_Mem_OEN, DIR = O, VEC = [0:0]
 PORT fpga_0_SRAM_256Kx32_Mem_CEN_pin = fpga_0_SRAM_256Kx32_Mem_CEN, DIR = O, VEC = [0:0]
 PORT fpga_0_SRAM_256Kx32_Mem_ADV_LDN_pin = fpga_0_SRAM_256Kx32_Mem_ADV_LDN, DIR = O
 PORT fpga_0_DDR_CLK_FB = ddr_feedback_s, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000
 PORT fpga_0_SRAM_CLOCK = sys_clk_s, DIR = O
 PORT sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000
 PORT sys_rst_pin = sys_rst_s, DIR = I, RST_POLARITY = 0, SIGIS = RST
 PORT PortName = PortConnector
 PORT PortName1 = PortConnector
 PORT PortName2 = PortConnector


BEGIN microblaze
 PARAMETER INSTANCE = microblaze_0
 PARAMETER HW_VER = 5.00.c
 PARAMETER C_USE_FPU = 0
 PARAMETER C_DEBUG_ENABLED = 1
 PARAMETER C_NUMBER_OF_PC_BRK = 2
 BUS_INTERFACE DLMB = dlmb
 BUS_INTERFACE ILMB = ilmb
 BUS_INTERFACE DOPB = mb_opb
 BUS_INTERFACE IOPB = mb_opb
 PORT DBG_CAPTURE = DBG_CAPTURE_s
 PORT DBG_CLK = DBG_CLK_s
 PORT DBG_REG_EN = DBG_REG_EN_s
 PORT DBG_TDI = DBG_TDI_s
 PORT DBG_TDO = DBG_TDO_s
 PORT DBG_UPDATE = DBG_UPDATE_s
END

BEGIN opb_v20
 PARAMETER INSTANCE = mb_opb
 PARAMETER HW_VER = 1.10.c
 PARAMETER C_EXT_RESET_HIGH = 0
 PORT SYS_Rst = sys_rst_s
 PORT OPB_Clk = sys_clk_s
END

BEGIN opb_mdm
 PARAMETER INSTANCE = debug_module
 PARAMETER HW_VER = 2.00.a
 PARAMETER C_MB_DBG_PORTS = 1
 PARAMETER C_USE_UART = 1
 PARAMETER C_UART_WIDTH = 8
 PARAMETER C_BASEADDR = 0x41400000
 PARAMETER C_HIGHADDR = 0x4140ffff
 BUS_INTERFACE SOPB = mb_opb
 PORT DBG_CAPTURE_0 = DBG_CAPTURE_s
 PORT DBG_CLK_0 = DBG_CLK_s
 PORT DBG_REG_EN_0 = DBG_REG_EN_s
 PORT DBG_TDI_0 = DBG_TDI_s
 PORT DBG_TDO_0 = DBG_TDO_s
 PORT DBG_UPDATE_0 = DBG_UPDATE_s
 PORT DBG_CAPTURE_1 = DBG_CAPTURE_s1
 PORT DBG_CLK_1 = DBG_CLK_s1
 PORT DBG_REG_EN_1 = DBG_REG_EN_s1
 PORT DBG_TDI_1 = DBG_TDI_s1
 PORT DBG_TDO_1 = DBG_TDO_s1
 PORT DBG_UPDATE_1 = DBG_UPDATE_s1
END

BEGIN lmb_v10
 PARAMETER INSTANCE = ilmb
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_EXT_RESET_HIGH = 0
 PORT SYS_Rst = sys_rst_s
 PORT LMB_Clk = sys_clk_s
END

BEGIN lmb_v10
 PARAMETER INSTANCE = dlmb
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_EXT_RESET_HIGH = 0
 PORT SYS_Rst = sys_rst_s
 PORT LMB_Clk = sys_clk_s
END

BEGIN lmb_bram_if_cntlr
 PARAMETER INSTANCE = dlmb_cntlr
 PARAMETER HW_VER = 2.00.a
 PARAMETER C_BASEADDR = 0x00000000
 PARAMETER C_HIGHADDR = 0x00001fff
 BUS_INTERFACE SLMB = dlmb
 BUS_INTERFACE BRAM_PORT = dlmb_port
END

BEGIN lmb_bram_if_cntlr
 PARAMETER INSTANCE = ilmb_cntlr
 PARAMETER HW_VER = 2.00.a
 PARAMETER C_BASEADDR = 0x00000000
 PARAMETER C_HIGHADDR = 0x00001fff
 BUS_INTERFACE SLMB = ilmb
 BUS_INTERFACE BRAM_PORT = ilmb_port
END

BEGIN bram_block
 PARAMETER INSTANCE = lmb_bram
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE PORTA = ilmb_port
 BUS_INTERFACE PORTB = dlmb_port
END

BEGIN opb_uartlite
 PARAMETER INSTANCE = RS232_Uart
 PARAMETER HW_VER = 1.00.b
 PARAMETER C_BAUDRATE = 9600
 PARAMETER C_DATA_BITS = 8
 PARAMETER C_ODD_PARITY = 0
 PARAMETER C_USE_PARITY = 0
 PARAMETER C_CLK_FREQ = 100000000
 PARAMETER C_BASEADDR = 0x40600000
 PARAMETER C_HIGHADDR = 0x4060ffff
 BUS_INTERFACE SOPB = mb_opb
 PORT RX = fpga_0_RS232_Uart_RX
 PORT TX = fpga_0_RS232_Uart_TX
END

BEGIN opb_ddr
 PARAMETER INSTANCE = DDR_SDRAM_64Mx32
 PARAMETER HW_VER = 2.00.c
 PARAMETER C_OPB_CLK_PERIOD_PS = 10000
 PARAMETER C_DDR_ASYNC_SUPPORT = 0
 PARAMETER C_REG_DIMM = 0
 PARAMETER C_DDR_TMRD = 20000
 PARAMETER C_DDR_TWR = 20000
 PARAMETER C_DDR_TRAS = 60000
 PARAMETER C_DDR_TRC = 90000
 PARAMETER C_DDR_TRFC = 80000
 PARAMETER C_DDR_TRCD = 30000
 PARAMETER C_DDR_TRRD = 15000
 PARAMETER C_DDR_TRP = 30000
 PARAMETER C_DDR_TREFC = 70300000
 PARAMETER C_DDR_TREFI = 7800000
 PARAMETER C_DDR_AWIDTH = 13
 PARAMETER C_DDR_COL_AWIDTH = 9
 PARAMETER C_DDR_BANK_AWIDTH = 2
 PARAMETER C_DDR_DWIDTH = 32
 PARAMETER C_MEM0_BASEADDR = 0x28000000
 PARAMETER C_MEM0_HIGHADDR = 0x2bffffff
 BUS_INTERFACE SOPB = mb_opb
 PORT DDR_Addr = fpga_0_DDR_SDRAM_64Mx32_DDR_Addr
 PORT DDR_BankAddr = fpga_0_DDR_SDRAM_64Mx32_DDR_BankAddr
 PORT DDR_CASn = fpga_0_DDR_SDRAM_64Mx32_DDR_CASn
 PORT DDR_CKE = fpga_0_DDR_SDRAM_64Mx32_DDR_CKE
 PORT DDR_CSn = fpga_0_DDR_SDRAM_64Mx32_DDR_CSn
 PORT DDR_RASn = fpga_0_DDR_SDRAM_64Mx32_DDR_RASn
 PORT DDR_WEn = fpga_0_DDR_SDRAM_64Mx32_DDR_WEn
 PORT DDR_DM = fpga_0_DDR_SDRAM_64Mx32_DDR_DM
 PORT DDR_DQS = fpga_0_DDR_SDRAM_64Mx32_DDR_DQS
 PORT DDR_DQ = fpga_0_DDR_SDRAM_64Mx32_DDR_DQ
 PORT DDR_Clk = fpga_0_DDR_SDRAM_64Mx32_DDR_Clk
 PORT DDR_Clkn = fpga_0_DDR_SDRAM_64Mx32_DDR_Clkn
 PORT Device_Clk90_in = clk_90_s
 PORT Device_Clk90_in_n = clk_90_n_s
 PORT Device_Clk = sys_clk_s
 PORT Device_Clk_n = sys_clk_n_s
 PORT DDR_Clk90_in = ddr_clk_90_s
 PORT DDR_Clk90_in_n = ddr_clk_90_n_s
END

BEGIN opb_emc
 PARAMETER INSTANCE = SRAM_256Kx32
 PARAMETER HW_VER = 2.00.a
 PARAMETER C_OPB_CLK_PERIOD_PS = 10000
 PARAMETER C_NUM_BANKS_MEM = 1
 PARAMETER C_MAX_MEM_WIDTH = 32
 PARAMETER C_INCLUDE_NEGEDGE_IOREGS = 1
 PARAMETER C_INCLUDE_DATAWIDTH_MATCHING_0 = 1
 PARAMETER C_MEM0_WIDTH = 32
 PARAMETER C_SYNCH_MEM_0 = 1
 PARAMETER C_TCEDV_PS_MEM_0 = 0
 PARAMETER C_TWC_PS_MEM_0 = 0
 PARAMETER C_TAVDV_PS_MEM_0 = 0
 PARAMETER C_TWP_PS_MEM_0 = 0
 PARAMETER C_THZCE_PS_MEM_0 = 0
 PARAMETER C_TLZWE_PS_MEM_0 = 0
 PARAMETER C_MEM0_BASEADDR = 0x2c000000
 PARAMETER C_MEM0_HIGHADDR = 0x2c0fffff
 BUS_INTERFACE SOPB = mb_opb
 PORT Mem_A = fpga_0_SRAM_256Kx32_Mem_A_split
 PORT Mem_BEN = fpga_0_SRAM_256Kx32_Mem_BEN
 PORT Mem_WEN = fpga_0_SRAM_256Kx32_Mem_WEN
 PORT Mem_DQ = fpga_0_SRAM_256Kx32_Mem_DQ
 PORT Mem_OEN = fpga_0_SRAM_256Kx32_Mem_OEN
 PORT Mem_CEN = fpga_0_SRAM_256Kx32_Mem_CEN
 PORT Mem_ADV_LDN = fpga_0_SRAM_256Kx32_Mem_ADV_LDN
END

BEGIN util_bus_split
 PARAMETER INSTANCE = SRAM_256Kx32_util_bus_split_2
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_SIZE_IN = 32
 PARAMETER C_LEFT_POS = 9
 PARAMETER C_SPLIT = 30
 PORT Sig = fpga_0_SRAM_256Kx32_Mem_A_split
 PORT Out1 = fpga_0_SRAM_256Kx32_Mem_A
END

BEGIN util_vector_logic
 PARAMETER INSTANCE = sysclk_inv
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_SIZE = 1
 PARAMETER C_OPERATION = not
 PORT Op1 = sys_clk_s
 PORT Res = sys_clk_n_s
END

BEGIN util_vector_logic
 PARAMETER INSTANCE = clk90_inv
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_SIZE = 1
 PARAMETER C_OPERATION = not
 PORT Op1 = clk_90_s
 PORT Res = clk_90_n_s
END

BEGIN util_vector_logic
 PARAMETER INSTANCE = ddr_clk90_inv
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_SIZE = 1
 PARAMETER C_OPERATION = not
 PORT Op1 = ddr_clk_90_s
 PORT Res = ddr_clk_90_n_s
END

BEGIN dcm_module
 PARAMETER INSTANCE = dcm_0
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_CLK0_BUF = TRUE
 PARAMETER C_CLK90_BUF = TRUE
 PARAMETER C_CLKIN_PERIOD = 10.000000
 PARAMETER C_CLK_FEEDBACK = 1X
 PARAMETER C_DLL_FREQUENCY_MODE = LOW
 PARAMETER C_EXT_RESET_HIGH = 1
 PORT CLKIN = dcm_clk_s
 PORT CLK0 = sys_clk_s
 PORT CLK90 = clk_90_s
 PORT CLKFB = sys_clk_s
 PORT RST = net_gnd
 PORT LOCKED = dcm_0_lock
END

BEGIN dcm_module
 PARAMETER INSTANCE = dcm_1
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_CLK0_BUF = TRUE
 PARAMETER C_CLK90_BUF = TRUE
 PARAMETER C_CLKIN_PERIOD = 10.000000
 PARAMETER C_CLK_FEEDBACK = 1X
 PARAMETER C_DLL_FREQUENCY_MODE = LOW
 PARAMETER C_PHASE_SHIFT = 12
 PARAMETER C_CLKOUT_PHASE_SHIFT = FIXED
 PARAMETER C_EXT_RESET_HIGH = 0
 PORT CLKIN = ddr_feedback_s
 PORT CLK90 = ddr_clk_90_s
 PORT CLK0 = dcm_1_FB
 PORT CLKFB = dcm_1_FB
 PORT RST = dcm_0_lock
 PORT LOCKED = dcm_1_lock
END

BEGIN microblaze
 PARAMETER INSTANCE = microblaze_1
 PARAMETER HW_VER = 5.00.c
 BUS_INTERFACE DOPB = mb_opb
 BUS_INTERFACE IOPB = mb_opb
 BUS_INTERFACE DLMB = lmb_v10_0
 BUS_INTERFACE ILMB = lmb_v10_1
 PORT DBG_CAPTURE = DBG_CAPTURE_s1
 PORT DBG_CLK = DBG_CLK_s1
 PORT DBG_REG_EN = DBG_REG_EN_s1
 PORT DBG_TDI = DBG_TDI_s1
 PORT DBG_TDO = DBG_TDO_s1
 PORT DBG_UPDATE = DBG_UPDATE_s1
END

BEGIN lmb_v10
 PARAMETER INSTANCE = lmb_v10_0
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_EXT_RESET_HIGH = 0
 PORT SYS_Rst = sys_rst_s
 PORT LMB_Clk = sys_clk_s
END

BEGIN lmb_v10
 PARAMETER INSTANCE = lmb_v10_1
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_EXT_RESET_HIGH = 0
 PORT SYS_Rst = sys_rst_s
 PORT LMB_Clk = sys_clk_s
END

BEGIN lmb_bram_if_cntlr
 PARAMETER INSTANCE = lmb_bram_if_cntlr_0
 PARAMETER HW_VER = 2.00.a
 PARAMETER C_BASEADDR = 0x00000000
 PARAMETER C_HIGHADDR = 0x00001fff
 BUS_INTERFACE SLMB = lmb_v10_0
 BUS_INTERFACE BRAM_PORT = lmb_bram_if_cntlr_0_BRAM_PORT
END

BEGIN lmb_bram_if_cntlr
 PARAMETER INSTANCE = lmb_bram_if_cntlr_1
 PARAMETER HW_VER = 2.00.a
 PARAMETER C_BASEADDR = 0x00000000
 PARAMETER C_HIGHADDR = 0x00001fff
 BUS_INTERFACE SLMB = lmb_v10_1
 BUS_INTERFACE BRAM_PORT = lmb_bram_if_cntlr_1_BRAM_PORT
END

BEGIN bram_block
 PARAMETER INSTANCE = bram_block_0
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE PORTA = lmb_bram_if_cntlr_0_BRAM_PORT
 BUS_INTERFACE PORTB = lmb_bram_if_cntlr_1_BRAM_PORT
END
 

Xilinx Employee
Xilinx Employee
6,316 Views
Registered: ‎08-02-2007

Re: Debugging multiple Microblaze with MDM

Hello,

 

I think a good point to start off would be to refer XAPP996. This would give an idea as how can we design a Dual Processor Based System.

 

It mite not help in solving this issue but can be taken as a reference.

 

Regards,

Hem.

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Visitor kuganv
Visitor
6,308 Views
Registered: ‎06-10-2008

Re: Debugging multiple Microblaze with MDM

Thanks hem_8030.

I have solved this problem by changing to PARAMETER C_MB_DBG_PORTS = 2.

Newbie mhamzahab
Newbie
1,783 Views
Registered: ‎11-17-2014

Re: Debugging multiple Microblaze with MDM

thanks man... i also found the solution by increasing number of debug ports

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