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Registered: ‎12-15-2016

Devicetree Generator Fails with AXI 10G Ethernet

Upgrading our design to 2017.3 have revealed a possible bug in device tree generator.
In 2017.2 the generator generated the following dtsi for the DMA part of a 10G design.

hier_10g_eth_axi_dma_0: dma@80020000 {
        #dma-cells = <1>;
        clock-names = "s_axi_lite_aclk", "m_axi_sg_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk";
        clocks = <&misc_clk_0>, <&misc_clk_0>, <&misc_clk_0>, <&misc_clk_0>;
        compatible = "xlnx,eth-dma";
        interrupt-parent = <&gic>;
        interrupts = <0 90 4 0 91 4>;
        reg = <0x0 0x80020000 0x0 0x10000>;
        xlnx,addrwidth = <0x24>;
        xlnx,include-sg ;
        dma-channel@80020000 {
                compatible = "xlnx,axi-dma-mm2s-channel";
                dma-channels = <0x1>;
                interrupts = <0 90 4>;
                xlnx,datawidth = <0x40>;
                xlnx,device-id = <0x0>;
                xlnx,include-dre ;
        };
        dma-channel@80020030 {
                compatible = "xlnx,axi-dma-s2mm-channel";
                dma-channels = <0x1>;
                interrupts = <0 91 4>;
                xlnx,datawidth = <0x40>;
                xlnx,device-id = <0x0>;
                xlnx,include-dre ;
        };
};


Switching to 2017.3 it generates the following DMA related dtsi and generates the error:
(phandle_references): Reference to non-existent node or label "hier_10g_eth_rx_data_fifo_0"

 

hier_10g_eth_axi_dma_0: dma@80020000 {
        #dma-cells = <1>;
        axistream-connected = <&hier_10g_eth_rx_data_fifo_0>;
        axistream-control-connected = <&hier_10g_eth_rx_data_fifo_0>;
        clock-names = "s_axi_lite_aclk", "m_axi_sg_aclk";
        clocks = <&misc_clk_0>, <&misc_clk_0>;
        compatible = "xlnx,eth-dma";
        interrupt-parent = <&gic>;
        interrupts = <0 90 4 0 91 4>;
        reg = <0x0 0x80020000 0x0 0x10000>;
        xlnx,include-dre ;
};

 

The source of this issue is commit – cc38c413fb748dec06eb57457505ed1e2ade6727

(Notice if i link to the commit on github Xilinx forum reject my post)
Reverting it fixes the dts - so it is like 2017.2 again

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