Does EDK tool requires both the NGC and VHDL file ofcorege elements?
when i generate a FPGA downloable bit file with MY_IP vhdl files along with both NGC & VHDL files of xilinx coregen elements(like FIFO , buffers), its working properly. later when i generate a FPGA downloable bit file with same MY_IP vhdl files along with only NGC files of xilinx coregenelements(like FIFO , buffers), its not working at all.Does EDK tool requires both the NGC and VHDL file of a xilinx corege elements in orderto generate workable bit file in EDK tool?
Yes, I think that EDK needs both NGC/EDF and VHDL files so as to work properly
.... When you import the peripheral you must indicate both HDL and Netlist files for the coregen elements and the tool will prompt you for both file types ...