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Participant
Participant
4,603 Views
Registered: ‎09-23-2008

Driving a PLB

Can a custom IP be read from and written to using only the default PLB slave signals:

Bus2IP_Clk 
Bus2IP_Reset
Bus2IP_Addr
Bus2IP_CS  
Bus2IP_RNW 
Bus2IP_Data
Bus2IP_BE  
Bus2IP_RdCE
Bus2IP_WrCE
IP2Bus_Data
IP2Bus_RdAck
IP2Bus_WrAck
IP2Bus_Error
Is there any documentation using these signals to respond to the PLB master?

 

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Participant
Participant
4,590 Views
Registered: ‎09-23-2008

I think I found the documentation I was looking for.

 

File is called plbv46_slave.pdf and was buried in      10.1/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_single_v1_01_a/doc/

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Xilinx Employee
Xilinx Employee
4,580 Views
Registered: ‎08-13-2007

You may also find this useful if you are looking for information that goes beyond what is in that datasheet:

http://www.xilinx.com/support/answers/30189.htm (128bitplbbus_v4.6.pdf - Where can I find the 128-bit PLB Bus Architecture Specifications from IBM?)

Cheers,

bt

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Participant
Participant
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Registered: ‎09-23-2008

I have read through the documentation and am trying to do a simple read from my IP to the PPC. The only thing I am able to read back is all zeroes. Any ideas? Here are important portions of my code.

 

    --CS declaration

    Bus2IP_CS  : in  std_logic_vector(0 to 0);

 

 

 

    slv_read_ack <= Bus2IP_CS(0) and Bus2IP_RNW;
    
    Test: process( Bus2IP_CLK ) is
    begin
        if Bus2IP_CLK'event and Bus2IP_CLK = '1' then
            case Bus2IP_Addr is
                when x"00000f00"    => slv_data_bus <= x"11110000";
                when x"00000f04"    => slv_data_bus <= x"22220000";
                when others            => slv_data_bus <= x"33330000";
            end case;
            
        end if;
    end process TEST;

 

    IP2Bus_Data  <=    slv_data_bus when slv_read_ack = '1' else
                                 x"deadc0de";

    IP2Bus_WrAck <= '0';
    IP2Bus_RdAck <= slv_read_ack;
    IP2Bus_Error <= '0';

 

 

My program only tries to read from address F00 and F04, no writing at all. According to timing diagram in plbv46_slave_single.pdf on page 14, as soon as Bus2IP_CS and Bus2IP_RNW are asserted I present my data with a read ack and things should be fine. But it appears I am timing out and the PLb returns all zeroes... Any thoughts?

 

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Contributor
Contributor
4,490 Views
Registered: ‎06-13-2008

I have the similar question and hoping anyone can give an answer.

 

tarzan

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