04-28-2008 12:56 AM
I am using XPS in ISE flow. I have some external ports (inputs/outputs/bi-dir ports) that go to pins and the
remaining will go to internal modules. There are 74 ports that are bi-dir, and thus iobuf are created in the system.v.
XST synthesis is clean, and but in Translate (ngdbuild) I am getting the following warnings :
INFO:NgdBuild:889 - Pad net 'ml505/iobuf_73/IO' is not connected to an external
port in this design. A new port 'IO' has been added and is connected to this
INFO:NgdBuild:889 - Pad net 'ml505/iobuf_72/IO' is not connected to an external
port in this design. A new port 'IO_x' has been added and is connected to
INFO:NgdBuild:889 - Pad net 'ml505/iobuf_71/IO' is not connected to an external
port in this design. A new port 'IO_x_x' has been added and is connected to
INFO:NgdBuild:889 - Pad net 'ml505/iobuf_70/IO' is not connected to an external
port in this design. A new port 'IO_x_x_x' has been added and is connected
to this signal.
INFO:NgdBuild:889 - Pad net 'ml505/iobuf_0/IO' is not connected to an external
port in this design. A new port
_x' has been added and is connected to this signal.
ERROR:ConstraintSystem:59 - Constraint <Net fpga_0_LEDs_8Bit_GPIO_IO_pin<0> LOC
= AE24;> [ise_ml505.ucf(32)]: NET "fpga_0_LEDs_8Bit_GPIO_IO_pin<0>" not
found. Please verify that:
1. The specified design element actually exists in the original design.
2. The specified object is spelled correctly in the constraint source file.
<There are more errors of the above type>
Other info that might be helpful
- Net fpga_0_LEDs_8Bit_GPIO_IO_pin<0> is bi-dir pin defined which has iobuf instantiated declared in system.v
- Net fpga_0_LEDs_8Bit_GPIO_IO_pin<0> is also defined in the ucf file.
04-28-2008 07:14 AM
Since you are implementing the design in ISE, can you please check that
1. You have the UCF copied to the ISE project.
2. These signals have the same name in the ISE top level.
It is likely that you have renamed these signals in the ISE top level while retiaining the UCF and since only the top level net names are checked, the tools are unable to find them.
04-28-2008 08:54 AM
I did add the ucf "add existing source" in ProjNav.
Also the name is exactly the same. I used "create template" from the xmp within ISE and then instantiated this to the
top level file.
Both the XST and TRANSLATE have option of "Insert I/O pads" check box. I have this box checked in both places
and I also have tried unchecking this but I get the same errors.
I also have changed the "Insert No Pads" set to '1' as recommended by another thread to make the xps project
appear as a submodule (instead of top).
04-28-2008 11:40 AM
I am getting a similar error:
ERROR:ConstraintSystem:59 - Constraint <NET "clk1" S>: NET "clk1" not found.
I got the error after editing my top level verilog file and my constraints file.
I removed all references to "clk1" from both files, and then I get the error.
It's looking like the "clk1" reference is "sticking", somewhere in the build process.
I created a new project using all the same files, and the build completes successfully.
Again, it looks like some "sticky" record-keeping by the build process.
04-28-2008 12:48 PM
Thanks mysterjoe. I will try this but,
What did you have set in XST and TRANSLADE for option "Insert I/O pads" ?
Also did you change your "Insert No Pads" set to '1' in the project xmp file ?
04-29-2008 08:01 AM
I did not find the options you mentioned in my base 10.1 installation (no service packs).
I am upgrading to SP1, I'll try that and let you know how it goes.
If SP1 fixes my problem, then you are probably chasing a different problem.
04-29-2008 10:09 AM
SP1 did not fix the problem, the behavior is the same.
I found a translate option "Create I/O pads from ports" , it is unchecked.
Is that what you are referring to? I can't find the exact option you mention in your post.
The same files build OK in a new project under 10.1, and also work in 9.2, so this looks like a functional regression for Xilinx.
I have this entry in my top-level verilog module declaration:
input wire clk1,
And I have this in my constraints file:
NET "clk1" LOC = "N9";
These are the only references to clk1. I can build the project with those entries.
When I comment those entries out of the top-level verilog and constraints file, I get the error.
04-29-2008 10:51 AM
Actually I made a very *silly* mistake. I had a port width mismatch. A 8-bit
bus coming out of xps was only 1-bit going to my pins. Once I fixed this,
and cleaned all the generated files and rerun, it works.