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Newbie
Newbie
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Registered: ‎12-12-2012

ELF Check fails

I took my EDK design and incorporated it as a submodule into my Top Level custom Verilog design. I was able to generate the bitstream etc and Export HW for SDK. I then tried making a project and Application in SDK using the system.bit & system.bmm files. But in SDK, when I tried Xilinx Tools -> Program FPGA I started getting this ELF Check error. I can only guess that putting the EDK module inside my Top Level module screwed up the path for the microblaze processor. However the .bmm file path looks correct : EdkTopAxi/AxiDMov2Mig_i//microblaze_0.

 

elfcheck -hw \

D:/FPGA/Scratch/PA/DisProc1/DisProc1.sdk/SDK/SDK_Export/AxiDMov2Mig_hw_platform/system.xml \

-mode bootload -mem BRAM -pe AxiDMov2Mig_i/microblaze_0 \

C:/Xilinx/14.3/ISE_DS/EDK/sw/lib/unknown_arch/unknown_bootloop.elf

elfcheck

Xilinx EDK 14.3 Build EDK_P.40xd

Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.

Command Line: elfcheck -hw

D:/FPGA/Scratch/PA/DisProc1/DisProc1.sdk/SDK/SDK_Export/AxiDMov2Mig_hw_platform/

system.xml -mode bootload -mem BRAM -pe AxiDMov2Mig_i/microblaze_0

C:/Xilinx/14.3/ISE_DS/EDK/sw/lib/unknown_arch/unknown_bootloop.elf

ELF file : C:/Xilinx/14.3/ISE_DS/EDK/sw/lib/unknown_arch/unknown_bootloop.elf

Processor AxiDMov2Mig_i/microblaze_0 NOT present in the Hardware System

Internal Error: Processor AxiDMov2Mig_i/microblaze_0 NOT present in the Hardware

System.

Programming the FPGA failed due to errors from elfcheck

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Anonymous
Not applicable
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Re: ELF Check fails

If you added the EDK as a xmp file, then the tools will pull in the BMM file during NDGBuild (this creates the back annotated BMM file). So you should be using the back annotated BMM file in SDK not the BMM file. Can you verify that this is true.

 

If it is not generated, can you right click on Translate in ISE, and process properties, under other option add the -bm system.bmm

 

Also, can you review the created back annotated bmm file (will have the name xxx_bd.bmm). To see if the hierarchy is correct. If you are usign the edk submodule, this will need an edded layer of hierarchy that may not be getting generated correctly. Also, make sure the tag is correct for the same reason. This can be checked in the BMM file, after the ADDRESS_MAP. this should be similar to <ise_top><system_i>, basically, it should include the top level ise name in the tag too.

 

However, I would imagine this would cause a data2mem issue (http://www.xilinx.com/support/answers/51180.htm)

 

 

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